src/main/scala/devices/spi/SPIPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.spi
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
   7
   8 class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
   9
  10   val sck = pingen()
  11   val dq  = Vec(4, pingen())
  12   val cs  = Vec(c.csWidth, pingen())
  13
  14   override def cloneType: this.type =
  15     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
  16
  17 }
  18
  19 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c) {
  20
  21   override def cloneType: this.type =
  22     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
  23
  24   def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
  25     syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
  26
  27     withClockAndReset(clock, reset) {
  28       sck.outputPin(spi.sck, ds = driveStrength)
  29
  30       (dq zip spi.dq).foreach {case (p, s) =>
  31         p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
  32         p.o.oe := s.oe
  33         p.o.ie := ~s.oe
  34         s.i := ShiftRegister(p.i.ival, syncStages)
  35       }
  36
  37       (cs zip spi.cs) foreach { case (c, s) =>
  38         c.outputPin(s, ds = driveStrength)
  39       }
  40     }
  41   }
  42 }