Initial commit.
[sifive-blocks.git] / src / main / scala / devices / spi / SPIRegs.scala
1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
3
4 object SPICRs {
5 val sckdiv = 0x00
6 val sckmode = 0x04
7 val csid = 0x10
8 val csdef = 0x14
9 val csmode = 0x18
10 val dcssck = 0x28
11 val dsckcs = 0x2a
12 val dintercs = 0x2c
13 val dinterxfr = 0x2e
14
15 val fmt = 0x40
16 val len = 0x42
17 val txfifo = 0x48
18 val rxfifo = 0x4c
19 val txmark = 0x50
20 val rxmark = 0x54
21
22 val insnmode = 0x60
23 val insnfmt = 0x64
24 val insnproto = 0x65
25 val insncmd = 0x66
26 val insnpad = 0x67
27
28 val ie = 0x70
29 val ip = 0x74
30 }