src/main/scala/devices/uart/UART.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import config._
   6 import regmapper._
   7 import uncore.tilelink2._
   8 import junctions._
   9 import util._
  10 import rocketchip.PeripheryBusConfig
  11 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
  12
  13 case class UARTConfig(
  14   address: BigInt,
  15   dataBits: Int = 8,
  16   stopBits: Int = 2,
  17   divisorBits: Int = 16,
  18   oversample: Int = 4,
  19   nSamples: Int = 3,
  20   nTxEntries: Int = 8,
  21   nRxEntries: Int = 8)
  22
  23 trait HasUARTParameters {
  24   val c: UARTConfig
  25   val uartDataBits = c.dataBits
  26   val uartStopBits = c.stopBits
  27   val uartDivisorBits = c.divisorBits
  28
  29   val uartOversample = c.oversample
  30   val uartOversampleFactor = 1 << uartOversample
  31   val uartNSamples = c.nSamples
  32
  33   val uartNTxEntries = c.nTxEntries
  34   val uartNRxEntries = c.nRxEntries
  35
  36   require(uartDivisorBits > uartOversample)
  37   require(uartOversampleFactor > uartNSamples)
  38 }
  39
  40 abstract class UARTModule(val c: UARTConfig)(implicit val p: Parameters)
  41     extends Module with HasUARTParameters
  42
  43 class UARTPortIO extends Bundle {
  44   val txd = Bool(OUTPUT)
  45   val rxd = Bool(INPUT)
  46 }
  47
  48 trait MixUARTParameters {
  49   val params: (UARTConfig, Parameters)
  50   val c = params._1
  51   implicit val p = params._2
  52 }
  53
  54 trait UARTTopBundle extends Bundle with MixUARTParameters with HasUARTParameters {
  55   val port = new UARTPortIO
  56 }
  57
  58 class UARTTx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
  59   val io = new Bundle {
  60     val en = Bool(INPUT)
  61     val in = Decoupled(Bits(width = uartDataBits)).flip
  62     val out = Bits(OUTPUT, 1)
  63     val div = UInt(INPUT, uartDivisorBits)
  64     val nstop = UInt(INPUT, log2Up(uartStopBits))
  65   }
  66
  67   val prescaler = Reg(init = UInt(0, uartDivisorBits))
  68   val pulse = (prescaler === UInt(0))
  69
  70   private val n = uartDataBits + 1
  71   val counter = Reg(init = UInt(0, log2Floor(n + uartStopBits) + 1))
  72   val shifter = Reg(Bits(width = n))
  73   val out = Reg(init = Bits(1, 1))
  74   io.out := out
  75
  76   val busy = (counter =/= UInt(0))
  77   io.in.ready := io.en && !busy
  78   when (io.in.fire()) {
  79     printf("%c", io.in.bits)
  80     shifter := Cat(io.in.bits, Bits(0, 1))
  81     counter := Mux1H((0 until uartStopBits).map(i =>
  82       (io.nstop === UInt(i)) -> UInt(n + i + 1)))
  83   }
  84   when (busy) {
  85     prescaler := Mux(pulse, io.div, prescaler - UInt(1))
  86   }
  87   when (pulse && busy) {
  88     counter := counter - UInt(1)
  89     shifter := Cat(Bits(1, 1), shifter >> 1)
  90     out := shifter(0)
  91   }
  92 }
  93
  94 class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
  95   val io = new Bundle {
  96     val en = Bool(INPUT)
  97     val in = Bits(INPUT, 1)
  98     val out = Valid(Bits(width = uartDataBits))
  99     val div = UInt(INPUT, uartDivisorBits)
 100   }
 101
 102   val debounce = Reg(init = UInt(0, 2))
 103   val debounce_max = (debounce === UInt(3))
 104   val debounce_min = (debounce === UInt(0))
 105
 106   val prescaler = Reg(init = UInt(0, uartDivisorBits - uartOversample))
 107   val start = Wire(init = Bool(false))
 108   val busy = Wire(init = Bool(false))
 109   val pulse = (prescaler === UInt(0)) && busy
 110
 111   when (busy) {
 112     prescaler := prescaler - UInt(1)
 113   }
 114   when (start || pulse) {
 115     prescaler := io.div >> uartOversample
 116   }
 117
 118   val sample = Reg(Bits(width = uartNSamples))
 119   val voter = new Majority(sample.toBools.toSet)
 120   when (pulse) {
 121     sample := Cat(sample, io.in)
 122   }
 123
 124   private val delay0 = (uartOversampleFactor + uartNSamples) >> 1
 125   private val delay1 = uartOversampleFactor
 126
 127   val timer = Reg(UInt(width = uartOversample + 1))
 128   val counter = Reg(UInt(width = log2Floor(uartDataBits) + 1))
 129   val shifter = Reg(Bits(width = uartDataBits))
 130   val expire = (timer === UInt(0)) && pulse
 131
 132   val sched = Wire(init = Bool(false))
 133   when (pulse) {
 134     timer := timer - UInt(1)
 135   }
 136   when (sched) {
 137     timer := UInt(delay1-1)
 138   }
 139
 140   val valid = Reg(init = Bool(false))
 141   valid := Bool(false)
 142   io.out.valid := valid
 143   io.out.bits := shifter
 144
 145   val (s_idle :: s_start :: s_data :: Nil) = Enum(UInt(), 3)
 146   val state = Reg(init = s_idle)
 147
 148   switch (state) {
 149     is (s_idle) {
 150       when (!(!io.in) && !debounce_min) {
 151         debounce := debounce - UInt(1)
 152       }
 153       when (!io.in) {
 154         debounce := debounce + UInt(1)
 155         when (debounce_max) {
 156           state := s_start
 157           start := Bool(true)
 158           timer := UInt(delay0-1)
 159         }
 160       }
 161     }
 162
 163     is (s_start) {
 164       busy := Bool(true)
 165       when (expire) {
 166         sched := Bool(true)
 167         when (voter.out) {
 168           state := s_idle
 169         } .otherwise {
 170           state := s_data
 171           counter := UInt(uartDataBits)
 172         }
 173       }
 174     }
 175
 176     is (s_data) {
 177       busy := Bool(true)
 178       when (expire) {
 179         counter := counter - UInt(1)
 180         when (counter === UInt(0)) {
 181           state := s_idle
 182           valid := Bool(true)
 183         } .otherwise {
 184           shifter := Cat(voter.out, shifter >> 1)
 185           sched := Bool(true)
 186         }
 187       }
 188     }
 189   }
 190
 191   when (!io.en) {
 192     debounce := UInt(0)
 193   }
 194 }
 195
 196 class UARTInterrupts extends Bundle {
 197   val rxwm = Bool()
 198   val txwm = Bool()
 199 }
 200
 201 trait UARTTopModule extends Module with MixUARTParameters with HasUARTParameters with HasRegMap {
 202   val io: UARTTopBundle
 203
 204   val txm = Module(new UARTTx(c))
 205   val txq = Module(new Queue(txm.io.in.bits, uartNTxEntries))
 206
 207   val rxm = Module(new UARTRx(c))
 208   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 209
 210   val divinit = 542 // (62.5MHz / 115200)
 211   val div = Reg(init = UInt(divinit, uartDivisorBits))
 212
 213   private val stopCountBits = log2Up(uartStopBits)
 214   private val txCountBits = log2Floor(uartNTxEntries) + 1
 215   private val rxCountBits = log2Floor(uartNRxEntries) + 1
 216
 217   val txen = Reg(init = Bool(false))
 218   val rxen = Reg(init = Bool(false))
 219   val txwm = Reg(init = UInt(0, txCountBits))
 220   val rxwm = Reg(init = UInt(0, rxCountBits))
 221   val nstop = Reg(init = UInt(0, stopCountBits))
 222
 223   txm.io.en := txen
 224   txm.io.in <> txq.io.deq
 225   txm.io.div := div
 226   txm.io.nstop := nstop
 227   io.port.txd := txm.io.out
 228
 229   rxm.io.en := rxen
 230   rxm.io.in := io.port.rxd
 231   rxq.io.enq <> rxm.io.out
 232   rxm.io.div := div
 233
 234   val ie = Reg(init = new UARTInterrupts().fromBits(Bits(0)))
 235   val ip = Wire(new UARTInterrupts)
 236
 237   ip.txwm := (txq.io.count < txwm)
 238   ip.rxwm := (rxq.io.count > rxwm)
 239   interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
 240
 241   regmap(
 242     UARTCtrlRegs.txfifo -> NonBlockingEnqueue(txq.io.enq),
 243     UARTCtrlRegs.rxfifo -> NonBlockingDequeue(rxq.io.deq),
 244
 245     UARTCtrlRegs.txctrl -> Seq(
 246       RegField(1, txen),
 247       RegField(stopCountBits, nstop)),
 248     UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen)),
 249     UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm)),
 250     UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm)),
 251
 252     UARTCtrlRegs.ie -> Seq(
 253       RegField(1, ie.txwm),
 254       RegField(1, ie.rxwm)),
 255
 256     UARTCtrlRegs.ip -> Seq(
 257       RegField.r(1, ip.txwm),
 258       RegField.r(1, ip.rxwm)),
 259
 260     UARTCtrlRegs.div -> Seq(
 261       RegField(uartDivisorBits, div))
 262   )
 263 }
 264
 265 class Majority(in: Set[Bool]) {
 266   private val n = (in.size >> 1) + 1
 267   private val clauses = in.subsets(n).map(_.reduce(_ && _))
 268   val out = clauses.reduce(_ || _)
 269 }
 270
 271 // Magic TL2 Incantation to create a TL2 Slave
 272 class UART(c: UARTConfig)(implicit val p: Parameters)
 273   extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
 274   new TLRegBundle((c, p), _)    with UARTTopBundle)(
 275   new TLRegModule((c, p), _, _) with UARTTopModule)