src/main/scala/devices/uart/UART.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Parameters
   6 import freechips.rocketchip.regmapper._
   7 import freechips.rocketchip.tilelink._
   8 import freechips.rocketchip.util._
   9
  10 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
  11
  12 case class UARTParams(
  13   address: BigInt,
  14   dataBits: Int = 8,
  15   stopBits: Int = 2,
  16   divisorInit: Int = 0,
  17   divisorBits: Int = 16,
  18   oversample: Int = 4,
  19   nSamples: Int = 3,
  20   nTxEntries: Int = 8,
  21   nRxEntries: Int = 8)
  22
  23 trait HasUARTParameters {
  24   def c: UARTParams
  25   def uartDataBits = c.dataBits
  26   def uartStopBits = c.stopBits
  27   def uartDivisorInit = c.divisorInit
  28   def uartDivisorBits = c.divisorBits
  29
  30   def uartOversample = c.oversample
  31   def uartOversampleFactor = 1 << uartOversample
  32   def uartNSamples = c.nSamples
  33
  34   def uartNTxEntries = c.nTxEntries
  35   def uartNRxEntries = c.nRxEntries
  36
  37   require(uartDivisorInit != 0) // should have been initialized during instantiation
  38   require(uartDivisorBits > uartOversample)
  39   require(uartOversampleFactor > uartNSamples)
  40 }
  41
  42 abstract class UARTModule(val c: UARTParams)(implicit val p: Parameters)
  43     extends Module with HasUARTParameters
  44
  45 class UARTPortIO extends Bundle {
  46   val txd = Bool(OUTPUT)
  47   val rxd = Bool(INPUT)
  48 }
  49
  50 trait HasUARTTopBundleContents extends Bundle {
  51   val port = new UARTPortIO
  52 }
  53
  54 class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
  55   val io = new Bundle {
  56     val en = Bool(INPUT)
  57     val in = Decoupled(Bits(width = uartDataBits)).flip
  58     val out = Bits(OUTPUT, 1)
  59     val div = UInt(INPUT, uartDivisorBits)
  60     val nstop = UInt(INPUT, log2Up(uartStopBits))
  61   }
  62
  63   val prescaler = Reg(init = UInt(0, uartDivisorBits))
  64   val pulse = (prescaler === UInt(0))
  65
  66   private val n = uartDataBits + 1
  67   val counter = Reg(init = UInt(0, log2Floor(n + uartStopBits) + 1))
  68   val shifter = Reg(Bits(width = n))
  69   val out = Reg(init = Bits(1, 1))
  70   io.out := out
  71
  72   val busy = (counter =/= UInt(0))
  73   io.in.ready := io.en && !busy
  74   when (io.in.fire()) {
  75     printf("%c", io.in.bits)
  76     shifter := Cat(io.in.bits, Bits(0, 1))
  77     counter := Mux1H((0 until uartStopBits).map(i =>
  78       (io.nstop === UInt(i)) -> UInt(n + i + 1)))
  79   }
  80   when (busy) {
  81     prescaler := Mux(pulse, io.div, prescaler - UInt(1))
  82   }
  83   when (pulse && busy) {
  84     counter := counter - UInt(1)
  85     shifter := Cat(Bits(1, 1), shifter >> 1)
  86     out := shifter(0)
  87   }
  88 }
  89
  90 class UARTRx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
  91   val io = new Bundle {
  92     val en = Bool(INPUT)
  93     val in = Bits(INPUT, 1)
  94     val out = Valid(Bits(width = uartDataBits))
  95     val div = UInt(INPUT, uartDivisorBits)
  96   }
  97
  98   val debounce = Reg(init = UInt(0, 2))
  99   val debounce_max = (debounce === UInt(3))
 100   val debounce_min = (debounce === UInt(0))
 101
 102   val prescaler = Reg(init = UInt(0, uartDivisorBits - uartOversample))
 103   val start = Wire(init = Bool(false))
 104   val busy = Wire(init = Bool(false))
 105   val pulse = (prescaler === UInt(0)) && busy
 106
 107   when (busy) {
 108     prescaler := prescaler - UInt(1)
 109   }
 110   when (start || pulse) {
 111     prescaler := io.div >> uartOversample
 112   }
 113
 114   val sample = Reg(Bits(width = uartNSamples))
 115   val voter = Majority(sample.toBools.toSet)
 116   when (pulse) {
 117     sample := Cat(sample, io.in)
 118   }
 119
 120   private val delay0 = (uartOversampleFactor + uartNSamples) >> 1
 121   private val delay1 = uartOversampleFactor
 122
 123   val timer = Reg(UInt(width = uartOversample + 1))
 124   val counter = Reg(UInt(width = log2Floor(uartDataBits) + 1))
 125   val shifter = Reg(Bits(width = uartDataBits))
 126   val expire = (timer === UInt(0)) && pulse
 127
 128   val sched = Wire(init = Bool(false))
 129   when (pulse) {
 130     timer := timer - UInt(1)
 131   }
 132   when (sched) {
 133     timer := UInt(delay1-1)
 134   }
 135
 136   val valid = Reg(init = Bool(false))
 137   valid := Bool(false)
 138   io.out.valid := valid
 139   io.out.bits := shifter
 140
 141   val (s_idle :: s_start :: s_data :: Nil) = Enum(UInt(), 3)
 142   val state = Reg(init = s_idle)
 143
 144   switch (state) {
 145     is (s_idle) {
 146       when (!(!io.in) && !debounce_min) {
 147         debounce := debounce - UInt(1)
 148       }
 149       when (!io.in) {
 150         debounce := debounce + UInt(1)
 151         when (debounce_max) {
 152           state := s_start
 153           start := Bool(true)
 154           timer := UInt(delay0-1)
 155         }
 156       }
 157     }
 158
 159     is (s_start) {
 160       busy := Bool(true)
 161       when (expire) {
 162         sched := Bool(true)
 163         when (voter) {
 164           state := s_idle
 165         } .otherwise {
 166           state := s_data
 167           counter := UInt(uartDataBits)
 168         }
 169       }
 170     }
 171
 172     is (s_data) {
 173       busy := Bool(true)
 174       when (expire) {
 175         counter := counter - UInt(1)
 176         when (counter === UInt(0)) {
 177           state := s_idle
 178           valid := Bool(true)
 179         } .otherwise {
 180           shifter := Cat(voter, shifter >> 1)
 181           sched := Bool(true)
 182         }
 183       }
 184     }
 185   }
 186
 187   when (!io.en) {
 188     debounce := UInt(0)
 189   }
 190 }
 191
 192 class UARTInterrupts extends Bundle {
 193   val rxwm = Bool()
 194   val txwm = Bool()
 195 }
 196
 197 trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
 198   val io: HasUARTTopBundleContents
 199   implicit val p: Parameters
 200   def params: UARTParams
 201   def c = params
 202
 203   val txm = Module(new UARTTx(params))
 204   val txq = Module(new Queue(txm.io.in.bits, uartNTxEntries))
 205
 206   val rxm = Module(new UARTRx(params))
 207   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 208
 209   val div = Reg(init = UInt(uartDivisorInit, uartDivisorBits))
 210
 211   private val stopCountBits = log2Up(uartStopBits)
 212   private val txCountBits = log2Floor(uartNTxEntries) + 1
 213   private val rxCountBits = log2Floor(uartNRxEntries) + 1
 214
 215   val txen = Reg(init = Bool(false))
 216   val rxen = Reg(init = Bool(false))
 217   val txwm = Reg(init = UInt(0, txCountBits))
 218   val rxwm = Reg(init = UInt(0, rxCountBits))
 219   val nstop = Reg(init = UInt(0, stopCountBits))
 220
 221   txm.io.en := txen
 222   txm.io.in <> txq.io.deq
 223   txm.io.div := div
 224   txm.io.nstop := nstop
 225   io.port.txd := txm.io.out
 226
 227   rxm.io.en := rxen
 228   rxm.io.in := io.port.rxd
 229   rxq.io.enq <> rxm.io.out
 230   rxm.io.div := div
 231
 232   val ie = Reg(init = new UARTInterrupts().fromBits(Bits(0)))
 233   val ip = Wire(new UARTInterrupts)
 234
 235   ip.txwm := (txq.io.count < txwm)
 236   ip.rxwm := (rxq.io.count > rxwm)
 237   interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
 238
 239   regmap(
 240     UARTCtrlRegs.txfifo -> NonBlockingEnqueue(txq.io.enq),
 241     UARTCtrlRegs.rxfifo -> NonBlockingDequeue(rxq.io.deq),
 242
 243     UARTCtrlRegs.txctrl -> Seq(
 244       RegField(1, txen),
 245       RegField(stopCountBits, nstop)),
 246     UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen)),
 247     UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm)),
 248     UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm)),
 249
 250     UARTCtrlRegs.ie -> Seq(
 251       RegField(1, ie.txwm),
 252       RegField(1, ie.rxwm)),
 253
 254     UARTCtrlRegs.ip -> Seq(
 255       RegField.r(1, ip.txwm),
 256       RegField.r(1, ip.rxwm)),
 257
 258     UARTCtrlRegs.div -> Seq(
 259       RegField(uartDivisorBits, div))
 260   )
 261 }
 262
 263 // Magic TL2 Incantation to create a TL2 UART
 264 class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
 265   extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
 266   new TLRegBundle(c, _)    with HasUARTTopBundleContents)(
 267   new TLRegModule(c, _, _) with HasUARTTopModuleContents)