src/main/scala/devices/uart/UARTPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   8 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
   9 import sifive.blocks.util.ShiftRegisterInit
  10
  11 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  12
  13 trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
  14   val uartParams = p(PeripheryUARTKey)
  15   val uarts = uartParams map { params =>
  16     val uart = LazyModule(new TLUART(pbus.beatBytes, params))
  17     uart.node := pbus.toVariableWidthSlaves
  18     ibus.fromSync := uart.intnode
  19     uart
  20   }
  21 }
  22
  23 trait HasPeripheryUARTBundle {
  24   val uarts: Vec[UARTPortIO]
  25
  26   def tieoffUARTs(dummy: Int = 1) {
  27     uarts.foreach { _.rxd := UInt(1) }
  28   }
  29
  30   def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
  31     val pins = Module(new UARTGPIOPort(syncStages))
  32     pins.io.uart <> u
  33     pins.io.pins
  34   }
  35 }
  36
  37 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
  38   val outer: HasPeripheryUART
  39   val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
  40
  41   (uarts zip outer.uarts).foreach { case (io, device) =>
  42     io <> device.module.io.port
  43   }
  44 }
  45
  46 class UARTPinsIO extends Bundle {
  47   val rxd = new GPIOPin
  48   val txd = new GPIOPin
  49 }
  50
  51 class UARTGPIOPort(syncStages: Int = 0) extends Module {
  52   val io = new Bundle{
  53     val uart = new UARTPortIO().flip()
  54     val pins = new UARTPinsIO
  55   }
  56
  57   GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
  58   val rxd = GPIOInputPinCtrl(io.pins.rxd)
  59   io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
  60 }