src/main/scala/devices/uart/UARTPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.config.Field
   7 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
   8 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
   9
  10 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  11
  12 trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
  13   private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
  14   val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
  15   val uarts = uartParams map { params =>
  16     val uart = LazyModule(new TLUART(pbus.beatBytes, params))
  17     uart.node := pbus.toVariableWidthSlaves
  18     ibus.fromSync := uart.intnode
  19     uart
  20   }
  21 }
  22
  23 trait HasPeripheryUARTBundle {
  24   val uart: Vec[UARTPortIO]
  25
  26   def tieoffUARTs(dummy: Int = 1) {
  27     uart.foreach { _.rxd := UInt(1) }
  28   }
  29
  30 }
  31
  32 trait HasPeripheryUARTModuleImp extends LazyModuleImp with HasPeripheryUARTBundle {
  33   val outer: HasPeripheryUART
  34   val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
  35
  36   (uart zip outer.uarts).foreach { case (io, device) =>
  37     io <> device.module.io.port
  38   }
  39 }