src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   6 import freechips.rocketchip.chip.HasSystemNetworks
   7
   8 trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks {
   9   val module: HasPeripheryXilinxVC707MIGModuleImp
  10
  11   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
  12   require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
  13   xilinxvc707mig.node := mem(0).node
  14 }
  15
  16 trait HasPeripheryXilinxVC707MIGBundle {
  17   val xilinxvc707mig: XilinxVC707MIGIO
  18   def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
  19     pads <> xilinxvc707mig
  20   }
  21 }
  22
  23 trait HasPeripheryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
  24     with HasPeripheryXilinxVC707MIGBundle {
  25   val outer: HasPeripheryXilinxVC707MIG
  26   val xilinxvc707mig = IO(new XilinxVC707MIGIO)
  27
  28   xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
  29 }