src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import diplomacy._
   6 import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
   7 import coreplex.BankedL2Config
   8
   9 trait PeripheryXilinxVC707MIG extends TopNetwork {
  10   val module: PeripheryXilinxVC707MIGModule
  11
  12   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
  13   require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
  14   val mem = Seq(xilinxvc707mig.node)
  15 }
  16
  17 trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
  18   val xilinxvc707mig = new XilinxVC707MIGIO
  19 }
  20
  21 trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
  22   val outer: PeripheryXilinxVC707MIG
  23   val io: PeripheryXilinxVC707MIGBundle
  24
  25   io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
  26 }