src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707pciex1
   3
   4 import Chisel._
   5 import diplomacy.{LazyModule, LazyMultiIOModuleImp}
   6 import rocketchip.HasSystemNetworks
   7 import uncore.tilelink2._
   8
   9 trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks {
  10   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
  11   private val intXing = LazyModule(new IntXing)
  12
  13   fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
  14   xilinxvc707pcie.slave   := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
  15   xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
  16   intBus.intnode := intXing.intnode
  17   intXing.intnode := xilinxvc707pcie.intnode
  18 }
  19
  20 trait HasPeripheryXilinxVC707PCIeX1Bundle {
  21   val xilinxvc707pcie: XilinxVC707PCIeX1IO
  22   def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
  23     pads <> xilinxvc707pcie
  24   }
  25 }
  26
  27 trait HasPeripheryXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
  28     with HasPeripheryXilinxVC707PCIeX1Bundle {
  29   val outer: HasPeripheryXilinxVC707PCIeX1
  30   val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
  31
  32   xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
  33
  34   outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
  35   outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
  36 }