src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707pciex1
   3
   4 import Chisel._
   5 import diplomacy.LazyModule
   6 import rocketchip.{
   7   HasTopLevelNetworks,
   8   HasTopLevelNetworksModule,
   9   HasTopLevelNetworksBundle
  10 }
  11 import uncore.tilelink2._
  12
  13 trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
  14
  15   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
  16   private val intXing = LazyModule(new IntXing)
  17
  18   fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
  19   xilinxvc707pcie.slave   := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
  20   xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
  21   intBus.intnode := intXing.intnode
  22   intXing.intnode := xilinxvc707pcie.intnode
  23 }
  24
  25 trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
  26   val xilinxvc707pcie = new XilinxVC707PCIeX1IO
  27 }
  28
  29 trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
  30   val outer: HasPeripheryXilinxVC707PCIeX1
  31   val io: HasPeripheryXilinxVC707PCIeX1Bundle
  32
  33   io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
  34
  35   outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
  36   outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
  37 }