Initial commit.
[sifive-blocks.git] / src / main / scala / ip / xilinx / ibufds_gte2 / ibufds_gte2.scala
1 // See LICENSE for license details.
2 package sifive.blocks.ip.xilinx.ibufds_gte2
3
4 import Chisel._
5
6 //IP : xilinx unisim IBUFDS_GTE2
7 //Differential Signaling Input Buffer
8 //unparameterized
9
10 class IBUFDS_GTE2 extends BlackBox {
11 val io = new Bundle {
12 val O = Bool(OUTPUT)
13 val ODIV2 = Bool(OUTPUT)
14 val CEB = Bool(INPUT)
15 val I = Bool(INPUT)
16 val IB = Bool(INPUT)
17 }
18 }