src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1
   3
   4 import Chisel._
   5 import config._
   6 import diplomacy._
   7 import uncore.axi4._
   8 import junctions._
   9
  10 // IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
  11 // Black Box
  12 // Signals named _exactly_ as per Vivado generated verilog
  13 // s : -{lock, cache, prot, qos}
  14
  15 trait VC707AXIToPCIeX1IOSerial extends Bundle {
  16   //serial external pins
  17   val pci_exp_txp           = Bits(OUTPUT,1)
  18   val pci_exp_txn           = Bits(OUTPUT,1)
  19   val pci_exp_rxp           = Bits(INPUT,1)
  20   val pci_exp_rxn           = Bits(INPUT,1)
  21 }
  22
  23 trait VC707AXIToPCIeX1IOClocksReset extends Bundle {
  24   //clock, reset, control
  25   val axi_aresetn           = Bool(INPUT)
  26   val axi_aclk_out          = Clock(OUTPUT)
  27   val axi_ctl_aclk_out      = Clock(OUTPUT)
  28   val mmcm_lock             = Bool(OUTPUT)
  29 }
  30
  31 //scalastyle:off
  32 //turn off linter: blackbox name must match verilog module
  33 class vc707axi_to_pcie_x1() extends BlackBox
  34 {
  35   val io = new Bundle with VC707AXIToPCIeX1IOSerial
  36                       with VC707AXIToPCIeX1IOClocksReset {
  37     //refclk
  38     val REFCLK                = Bool(INPUT)
  39
  40     //clock, reset, control
  41     val INTX_MSI_Request      = Bool(INPUT)
  42     val INTX_MSI_Grant        = Bool(OUTPUT)
  43     val MSI_enable            = Bool(OUTPUT)
  44     val MSI_Vector_Num        = Bits(INPUT,5)
  45     val MSI_Vector_Width      = Bits(OUTPUT,3)
  46
  47     //interrupt
  48     val interrupt_out         = Bool(OUTPUT)
  49
  50     //axi slave
  51     //-{lock, cache, prot, qos}
  52     //slave interface write address
  53     val s_axi_awid            = Bits(INPUT,4)
  54     val s_axi_awaddr          = Bits(INPUT,32)
  55     val s_axi_awregion        = Bits(INPUT,4)
  56     val s_axi_awlen           = Bits(INPUT,8)
  57     val s_axi_awsize          = Bits(INPUT,3)
  58     val s_axi_awburst         = Bits(INPUT,2)
  59     //val s_axi_awlock        = Bool(INPUT)
  60     //val s_axi_awcache       = Bits(INPUT,4)
  61     //val s_axi_awprot        = Bits(INPUT,3)
  62     //val s_axi_awqos         = Bits(INPUT,4)
  63     val s_axi_awvalid         = Bool(INPUT)
  64     val s_axi_awready         = Bool(OUTPUT)
  65     //slave interface write data
  66     val s_axi_wdata           = Bits(INPUT,64)
  67     val s_axi_wstrb           = Bits(INPUT,8)
  68     val s_axi_wlast           = Bool(INPUT)
  69     val s_axi_wvalid          = Bool(INPUT)
  70     val s_axi_wready          = Bool(OUTPUT)
  71     //slave interface write response
  72     val s_axi_bready          = Bool(INPUT)
  73     val s_axi_bid             = Bits(OUTPUT,4)
  74     val s_axi_bresp           = Bits(OUTPUT,2)
  75     val s_axi_bvalid          = Bool(OUTPUT)
  76     //slave interface read address
  77     val s_axi_arid            = Bits(INPUT,4)
  78     val s_axi_araddr          = Bits(INPUT,32)
  79     val s_axi_arregion        = Bits(INPUT,4)
  80     val s_axi_arlen           = Bits(INPUT,8)
  81     val s_axi_arsize          = Bits(INPUT,3)
  82     val s_axi_arburst         = Bits(INPUT,2)
  83     //val s_axi_arlock        = Bits(INPUT,1)
  84     //val s_axi_arcache       = Bits(INPUT,4)
  85     //val s_axi_arprot        = Bits(INPUT,3)
  86     //val s_axi_arqos         = Bits(INPUT,4)
  87     val s_axi_arvalid         = Bool(INPUT)
  88     val s_axi_arready         = Bool(OUTPUT)
  89     //slave interface read data
  90     val s_axi_rready          = Bool(INPUT)
  91     val s_axi_rid             = Bits(OUTPUT,4)
  92     val s_axi_rdata           = Bits(OUTPUT,64)
  93     val s_axi_rresp           = Bits(OUTPUT,2)
  94     val s_axi_rlast           = Bool(OUTPUT)
  95     val s_axi_rvalid          = Bool(OUTPUT)
  96
  97     //axi master
  98     //-{id,region,qos}
  99     //slave interface write address ports
 100     //val m_axi_awid          = Bits(OUTPUT,4)
 101     val m_axi_awaddr          = Bits(OUTPUT,32)
 102     //val m_axi_awregion      = Bits(OUTPUT,4)
 103     val m_axi_awlen           = Bits(OUTPUT,8)
 104     val m_axi_awsize          = Bits(OUTPUT,3)
 105     val m_axi_awburst         = Bits(OUTPUT,2)
 106     val m_axi_awlock          = Bool(OUTPUT)
 107     val m_axi_awcache         = Bits(OUTPUT,4)
 108     val m_axi_awprot          = Bits(OUTPUT,3)
 109     //val m_axi_awqos         = Bits(OUTPUT,4)
 110     val m_axi_awvalid         = Bool(OUTPUT)
 111     val m_axi_awready         = Bool(INPUT)
 112     //slave interface write data ports
 113     val m_axi_wdata           = Bits(OUTPUT,64)
 114     val m_axi_wstrb           = Bits(OUTPUT,8)
 115     val m_axi_wlast           = Bool(OUTPUT)
 116     val m_axi_wvalid          = Bool(OUTPUT)
 117     val m_axi_wready          = Bool(INPUT)
 118     //slave interface write response ports
 119     val m_axi_bready          = Bool(OUTPUT)
 120     //val m_axi_bid           = Bits(INPUT,4)
 121     val m_axi_bresp           = Bits(INPUT,2)
 122     val m_axi_bvalid          = Bool(INPUT)
 123     //slave interface read address ports
 124     //val m_axi_arid          = Bits(OUTPUT,4)
 125     val m_axi_araddr          = Bits(OUTPUT,32)
 126     //val m_axi_arregion      = Bits(OUTPUT,4)
 127     val m_axi_arlen           = Bits(OUTPUT,8)
 128     val m_axi_arsize          = Bits(OUTPUT,3)
 129     val m_axi_arburst         = Bits(OUTPUT,2)
 130     val m_axi_arlock          = Bits(OUTPUT,1)
 131     val m_axi_arcache         = Bits(OUTPUT,4)
 132     val m_axi_arprot          = Bits(OUTPUT,3)
 133     //val m_axi_arqos         = Bits(OUTPUT,4)
 134     val m_axi_arvalid         = Bool(OUTPUT)
 135     val m_axi_arready         = Bool(INPUT)
 136     //slave interface read data ports
 137     val m_axi_rready          = Bool(OUTPUT)
 138     //val m_axi_rid           = Bits(INPUT,4)
 139     val m_axi_rdata           = Bits(INPUT,64)
 140     val m_axi_rresp           = Bits(INPUT,2)
 141     val m_axi_rlast           = Bool(INPUT)
 142     val m_axi_rvalid          = Bool(INPUT)
 143
 144     //axi lite slave for control
 145     val s_axi_ctl_awaddr      = Bits(INPUT,32)
 146     val s_axi_ctl_awvalid     = Bool(INPUT)
 147     val s_axi_ctl_awready     = Bool(OUTPUT)
 148     val s_axi_ctl_wdata       = Bits(INPUT,32)
 149     val s_axi_ctl_wstrb       = Bits(INPUT,4)
 150     val s_axi_ctl_wvalid      = Bool(INPUT)
 151     val s_axi_ctl_wready      = Bool(OUTPUT)
 152     val s_axi_ctl_bresp       = Bits(OUTPUT,2)
 153     val s_axi_ctl_bvalid      = Bool(OUTPUT)
 154     val s_axi_ctl_bready      = Bool(INPUT)
 155     val s_axi_ctl_araddr      = Bits(INPUT,32)
 156     val s_axi_ctl_arvalid     = Bool(INPUT)
 157     val s_axi_ctl_arready     = Bool(OUTPUT)
 158     val s_axi_ctl_rdata       = Bits(OUTPUT,32)
 159     val s_axi_ctl_rresp       = Bits(OUTPUT,2)
 160     val s_axi_ctl_rvalid      = Bool(OUTPUT)
 161     val s_axi_ctl_rready      = Bool(INPUT)
 162  }
 163 }
 164 //scalastyle:off
 165
 166 //wrap vc707_axi_to_pcie_x1 black box in Nasti Bundles
 167
 168 class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
 169 {
 170   val slave = AXI4SlaveNode(AXI4SlavePortParameters(
 171     slaves = Seq(AXI4SlaveParameters(
 172       address       = List(AddressSet(0x60000000L, 0x1fffffffL)),
 173       executable    = true,
 174       supportsWrite = TransferSizes(1, 256),
 175       supportsRead  = TransferSizes(1, 256),
 176       interleavedId = Some(0))), // the Xilinx IP is friendly
 177     beatBytes = 8))
 178
 179   val control = AXI4SlaveNode(AXI4SlavePortParameters(
 180     slaves = Seq(AXI4SlaveParameters(
 181       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
 182       supportsWrite = TransferSizes(1, 4),
 183       supportsRead  = TransferSizes(1, 4),
 184       interleavedId = Some(0))), // no read interleaving b/c AXI-lite
 185     beatBytes = 4))
 186
 187   val master = AXI4MasterNode(AXI4MasterPortParameters(
 188     masters = Seq(AXI4MasterParameters(
 189       id      = IdRange(0, 1),
 190       aligned = false))))
 191
 192   lazy val module = new LazyModuleImp(this) {
 193     // The master on the control port must be AXI-lite
 194     require (control.edgesIn(0).master.endId == 1)
 195     // Must have exactly the right number of idBits
 196     require (slave.edgesIn(0).bundle.idBits == 4)
 197
 198     class VC707AXIToPCIeX1IOBundle extends Bundle with VC707AXIToPCIeX1IOSerial
 199                                                   with VC707AXIToPCIeX1IOClocksReset;
 200
 201     val io = new Bundle {
 202       val port = new VC707AXIToPCIeX1IOBundle
 203       val slave_in = slave.bundleIn
 204       val control_in = control.bundleIn
 205       val master_out = master.bundleOut
 206       val REFCLK = Bool(INPUT)
 207       val interrupt_out = Bool(OUTPUT)
 208     }
 209
 210     val blackbox = Module(new vc707axi_to_pcie_x1)
 211
 212     val s = io.slave_in(0)
 213     val c = io.control_in(0)
 214     val m = io.master_out(0)
 215
 216     //to top level
 217     blackbox.io.axi_aresetn         := io.port.axi_aresetn
 218     io.port.axi_aclk_out            := blackbox.io.axi_aclk_out
 219     io.port.axi_ctl_aclk_out        := blackbox.io.axi_ctl_aclk_out
 220     io.port.mmcm_lock               := blackbox.io.mmcm_lock
 221     io.port.pci_exp_txp             := blackbox.io.pci_exp_txp
 222     io.port.pci_exp_txn             := blackbox.io.pci_exp_txn
 223     blackbox.io.pci_exp_rxp         := io.port.pci_exp_rxp
 224     blackbox.io.pci_exp_rxn         := io.port.pci_exp_rxn
 225     io.interrupt_out                := blackbox.io.interrupt_out
 226     blackbox.io.REFCLK              := io.REFCLK
 227
 228     //s
 229     //AXI4 signals ordered as per AXI4 Specification (Release D) Section A.2
 230     //-{lock, cache, prot, qos}
 231     //-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
 232     //global signals
 233     //aclk                          :=
 234     //aresetn                       :=
 235     //slave interface write address
 236     blackbox.io.s_axi_awid          := s.aw.bits.id
 237     blackbox.io.s_axi_awaddr        := s.aw.bits.addr
 238     blackbox.io.s_axi_awlen         := s.aw.bits.len
 239     blackbox.io.s_axi_awsize        := s.aw.bits.size
 240     blackbox.io.s_axi_awburst       := s.aw.bits.burst
 241     //blackbox.io.s_axi_awlock      := s.aw.bits.lock
 242     //blackbox.io.s_axi_awcache     := s.aw.bits.cache
 243     //blackbox.io.s_axi_awprot      := s.aw.bits.prot
 244     //blackbox.io.s_axi_awqos       := s.aw.bits.qos
 245     blackbox.io.s_axi_awregion      := UInt(0)
 246     //blackbox.io.awuser            := s.aw.bits.user
 247     blackbox.io.s_axi_awvalid       := s.aw.valid
 248     s.aw.ready                   := blackbox.io.s_axi_awready
 249     //slave interface write data ports
 250     //blackbox.io.s_axi_wid         := s.w.bits.id
 251     blackbox.io.s_axi_wdata         := s.w.bits.data
 252     blackbox.io.s_axi_wstrb         := s.w.bits.strb
 253     blackbox.io.s_axi_wlast         := s.w.bits.last
 254     //blackbox.io.s_axi_wuser       := s.w.bits.user
 255     blackbox.io.s_axi_wvalid        := s.w.valid
 256     s.w.ready                    := blackbox.io.s_axi_wready
 257     //slave interface write response
 258     s.b.bits.id                  := blackbox.io.s_axi_bid
 259     s.b.bits.resp                := blackbox.io.s_axi_bresp
 260     //s.b.bits.user              := blackbox.io.s_axi_buser
 261     s.b.valid                    := blackbox.io.s_axi_bvalid
 262     blackbox.io.s_axi_bready        := s.b.ready
 263     //slave AXI interface read address ports
 264     blackbox.io.s_axi_arid          := s.ar.bits.id
 265     blackbox.io.s_axi_araddr        := s.ar.bits.addr
 266     blackbox.io.s_axi_arlen         := s.ar.bits.len
 267     blackbox.io.s_axi_arsize        := s.ar.bits.size
 268     blackbox.io.s_axi_arburst       := s.ar.bits.burst
 269     //blackbox.io.s_axi_arlock      := s.ar.bits.lock
 270     //blackbox.io.s_axi_arcache     := s.ar.bits.cache
 271     //blackbox.io.s_axi_arprot      := s.ar.bits.prot
 272     //blackbox.io.s_axi_arqos       := s.ar.bits.qos
 273     blackbox.io.s_axi_arregion      := UInt(0)
 274     //blackbox.io.s_axi_aruser      := s.ar.bits.user
 275     blackbox.io.s_axi_arvalid       := s.ar.valid
 276     s.ar.ready                   := blackbox.io.s_axi_arready
 277     //slave AXI interface read data ports
 278     s.r.bits.id                  := blackbox.io.s_axi_rid
 279     s.r.bits.data                := blackbox.io.s_axi_rdata
 280     s.r.bits.resp                := blackbox.io.s_axi_rresp
 281     s.r.bits.last                := blackbox.io.s_axi_rlast
 282     //s.r.bits.ruser             := blackbox.io.s_axi_ruser
 283     s.r.valid                    := blackbox.io.s_axi_rvalid
 284     blackbox.io.s_axi_rready        := s.r.ready
 285
 286     //ctl
 287     //axi-lite slave interface write address
 288     blackbox.io.s_axi_ctl_awaddr    := c.aw.bits.addr
 289     blackbox.io.s_axi_ctl_awvalid   := c.aw.valid
 290     c.aw.ready                 := blackbox.io.s_axi_ctl_awready
 291     //axi-lite slave interface write data ports
 292     blackbox.io.s_axi_ctl_wdata     := c.w.bits.data
 293     blackbox.io.s_axi_ctl_wstrb     := c.w.bits.strb
 294     blackbox.io.s_axi_ctl_wvalid    := c.w.valid
 295     c.w.ready                  := blackbox.io.s_axi_ctl_wready
 296     //axi-lite slave interface write response
 297     blackbox.io.s_axi_ctl_bready    := c.b.ready
 298     c.b.bits.id                := UInt(0)
 299     c.b.bits.resp              := blackbox.io.s_axi_ctl_bresp
 300     c.b.valid                  := blackbox.io.s_axi_ctl_bvalid
 301     //axi-lite slave AXI interface read address ports
 302     blackbox.io.s_axi_ctl_araddr    := c.ar.bits.addr
 303     blackbox.io.s_axi_ctl_arvalid   := c.ar.valid
 304     c.ar.ready                 := blackbox.io.s_axi_ctl_arready
 305     //slave AXI interface read data ports
 306     blackbox.io.s_axi_ctl_rready    := c.r.ready
 307     c.r.bits.id                := UInt(0)
 308     c.r.bits.data              := blackbox.io.s_axi_ctl_rdata
 309     c.r.bits.resp              := blackbox.io.s_axi_ctl_rresp
 310     c.r.bits.last              := Bool(true)
 311     c.r.valid                  := blackbox.io.s_axi_ctl_rvalid
 312
 313     //m
 314     //AXI4 signals ordered per AXI4 Specification (Release D) Section A.2
 315     //-{id,region,qos}
 316     //-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
 317     //global signals
 318     //aclk                          :=
 319     //aresetn                       :=
 320     //master interface write address
 321     m.aw.bits.id                 := UInt(0)
 322     m.aw.bits.addr               := blackbox.io.m_axi_awaddr
 323     m.aw.bits.len                := blackbox.io.m_axi_awlen
 324     m.aw.bits.size               := blackbox.io.m_axi_awsize
 325     m.aw.bits.burst              := blackbox.io.m_axi_awburst
 326     m.aw.bits.lock               := blackbox.io.m_axi_awlock
 327     m.aw.bits.cache              := blackbox.io.m_axi_awcache
 328     m.aw.bits.prot               := blackbox.io.m_axi_awprot
 329     m.aw.bits.qos                := UInt(0)
 330     //m.aw.bits.region           := blackbox.io.m_axi_awregion
 331     //m.aw.bits.user             := blackbox.io.m_axi_awuser
 332     m.aw.valid                   := blackbox.io.m_axi_awvalid
 333     blackbox.io.m_axi_awready    := m.aw.ready
 334
 335     //master interface write data ports
 336     m.w.bits.data                := blackbox.io.m_axi_wdata
 337     m.w.bits.strb                := blackbox.io.m_axi_wstrb
 338     m.w.bits.last                := blackbox.io.m_axi_wlast
 339     //m.w.bits.user              := blackbox.io.m_axi_wuser
 340     m.w.valid                    := blackbox.io.m_axi_wvalid
 341     blackbox.io.m_axi_wready     := m.w.ready
 342
 343     //master interface write response
 344     //blackbox.io.m_axi_bid      := m.b.bits.id
 345     blackbox.io.m_axi_bresp      := m.b.bits.resp
 346     //blackbox.io.m_axi_buser    := m.b.bits.user
 347     blackbox.io.m_axi_bvalid     := m.b.valid
 348     m.b.ready                    := blackbox.io.m_axi_bready
 349
 350     //master AXI interface read address ports
 351     m.ar.bits.id                 := UInt(0)
 352     m.ar.bits.addr               := blackbox.io.m_axi_araddr
 353     m.ar.bits.len                := blackbox.io.m_axi_arlen
 354     m.ar.bits.size               := blackbox.io.m_axi_arsize
 355     m.ar.bits.burst              := blackbox.io.m_axi_arburst
 356     m.ar.bits.lock               := blackbox.io.m_axi_arlock
 357     m.ar.bits.cache              := blackbox.io.m_axi_arcache
 358     m.ar.bits.prot               := blackbox.io.m_axi_arprot
 359     m.ar.bits.qos                := UInt(0)
 360     //m.ar.bits.region           := blackbox.io.m_axi_arregion
 361     //m.ar.bits.user             := blackbox.io.s_axi_aruser
 362     m.ar.valid                   := blackbox.io.m_axi_arvalid
 363     blackbox.io.m_axi_arready    := m.ar.ready
 364
 365     //master AXI interface read data ports
 366     //blackbox.io.m_axi_rid      := m.r.bits.id
 367     blackbox.io.m_axi_rdata      := m.r.bits.data
 368     blackbox.io.m_axi_rresp      := m.r.bits.resp
 369     blackbox.io.m_axi_rlast      := m.r.bits.last
 370     //blackbox.io.s_axi_ruser    := s.bits.ruser
 371     blackbox.io.m_axi_rvalid     := m.r.valid
 372     m.r.ready                    := blackbox.io.m_axi_rready
 373   }
 374 }