src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1
   3
   4 import Chisel._
   5 import config._
   6 import diplomacy._
   7 import uncore.axi4._
   8 import uncore.tilelink2.{IntSourceNode, IntSourcePortSimple}
   9 import junctions._
  10
  11 // IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
  12 // Black Box
  13 // Signals named _exactly_ as per Vivado generated verilog
  14 // s : -{lock, cache, prot, qos}
  15
  16 trait VC707AXIToPCIeX1IOSerial extends Bundle {
  17   //serial external pins
  18   val pci_exp_txp           = Bits(OUTPUT,1)
  19   val pci_exp_txn           = Bits(OUTPUT,1)
  20   val pci_exp_rxp           = Bits(INPUT,1)
  21   val pci_exp_rxn           = Bits(INPUT,1)
  22 }
  23
  24 trait VC707AXIToPCIeX1IOClocksReset extends Bundle {
  25   //clock, reset, control
  26   val axi_aresetn           = Bool(INPUT)
  27   val axi_aclk_out          = Clock(OUTPUT)
  28   val axi_ctl_aclk_out      = Clock(OUTPUT)
  29   val mmcm_lock             = Bool(OUTPUT)
  30 }
  31
  32 //scalastyle:off
  33 //turn off linter: blackbox name must match verilog module
  34 class vc707axi_to_pcie_x1() extends BlackBox
  35 {
  36   val io = new Bundle with VC707AXIToPCIeX1IOSerial
  37                       with VC707AXIToPCIeX1IOClocksReset {
  38     //refclk
  39     val REFCLK                = Bool(INPUT)
  40
  41     //clock, reset, control
  42     val INTX_MSI_Request      = Bool(INPUT)
  43     val INTX_MSI_Grant        = Bool(OUTPUT)
  44     val MSI_enable            = Bool(OUTPUT)
  45     val MSI_Vector_Num        = Bits(INPUT,5)
  46     val MSI_Vector_Width      = Bits(OUTPUT,3)
  47
  48     //interrupt
  49     val interrupt_out         = Bool(OUTPUT)
  50
  51     //axi slave
  52     //-{lock, cache, prot, qos}
  53     //slave interface write address
  54     val s_axi_awid            = Bits(INPUT,4)
  55     val s_axi_awaddr          = Bits(INPUT,32)
  56     val s_axi_awregion        = Bits(INPUT,4)
  57     val s_axi_awlen           = Bits(INPUT,8)
  58     val s_axi_awsize          = Bits(INPUT,3)
  59     val s_axi_awburst         = Bits(INPUT,2)
  60     //val s_axi_awlock        = Bool(INPUT)
  61     //val s_axi_awcache       = Bits(INPUT,4)
  62     //val s_axi_awprot        = Bits(INPUT,3)
  63     //val s_axi_awqos         = Bits(INPUT,4)
  64     val s_axi_awvalid         = Bool(INPUT)
  65     val s_axi_awready         = Bool(OUTPUT)
  66     //slave interface write data
  67     val s_axi_wdata           = Bits(INPUT,64)
  68     val s_axi_wstrb           = Bits(INPUT,8)
  69     val s_axi_wlast           = Bool(INPUT)
  70     val s_axi_wvalid          = Bool(INPUT)
  71     val s_axi_wready          = Bool(OUTPUT)
  72     //slave interface write response
  73     val s_axi_bready          = Bool(INPUT)
  74     val s_axi_bid             = Bits(OUTPUT,4)
  75     val s_axi_bresp           = Bits(OUTPUT,2)
  76     val s_axi_bvalid          = Bool(OUTPUT)
  77     //slave interface read address
  78     val s_axi_arid            = Bits(INPUT,4)
  79     val s_axi_araddr          = Bits(INPUT,32)
  80     val s_axi_arregion        = Bits(INPUT,4)
  81     val s_axi_arlen           = Bits(INPUT,8)
  82     val s_axi_arsize          = Bits(INPUT,3)
  83     val s_axi_arburst         = Bits(INPUT,2)
  84     //val s_axi_arlock        = Bits(INPUT,1)
  85     //val s_axi_arcache       = Bits(INPUT,4)
  86     //val s_axi_arprot        = Bits(INPUT,3)
  87     //val s_axi_arqos         = Bits(INPUT,4)
  88     val s_axi_arvalid         = Bool(INPUT)
  89     val s_axi_arready         = Bool(OUTPUT)
  90     //slave interface read data
  91     val s_axi_rready          = Bool(INPUT)
  92     val s_axi_rid             = Bits(OUTPUT,4)
  93     val s_axi_rdata           = Bits(OUTPUT,64)
  94     val s_axi_rresp           = Bits(OUTPUT,2)
  95     val s_axi_rlast           = Bool(OUTPUT)
  96     val s_axi_rvalid          = Bool(OUTPUT)
  97
  98     //axi master
  99     //-{id,region,qos}
 100     //slave interface write address ports
 101     //val m_axi_awid          = Bits(OUTPUT,4)
 102     val m_axi_awaddr          = Bits(OUTPUT,32)
 103     //val m_axi_awregion      = Bits(OUTPUT,4)
 104     val m_axi_awlen           = Bits(OUTPUT,8)
 105     val m_axi_awsize          = Bits(OUTPUT,3)
 106     val m_axi_awburst         = Bits(OUTPUT,2)
 107     val m_axi_awlock          = Bool(OUTPUT)
 108     val m_axi_awcache         = Bits(OUTPUT,4)
 109     val m_axi_awprot          = Bits(OUTPUT,3)
 110     //val m_axi_awqos         = Bits(OUTPUT,4)
 111     val m_axi_awvalid         = Bool(OUTPUT)
 112     val m_axi_awready         = Bool(INPUT)
 113     //slave interface write data ports
 114     val m_axi_wdata           = Bits(OUTPUT,64)
 115     val m_axi_wstrb           = Bits(OUTPUT,8)
 116     val m_axi_wlast           = Bool(OUTPUT)
 117     val m_axi_wvalid          = Bool(OUTPUT)
 118     val m_axi_wready          = Bool(INPUT)
 119     //slave interface write response ports
 120     val m_axi_bready          = Bool(OUTPUT)
 121     //val m_axi_bid           = Bits(INPUT,4)
 122     val m_axi_bresp           = Bits(INPUT,2)
 123     val m_axi_bvalid          = Bool(INPUT)
 124     //slave interface read address ports
 125     //val m_axi_arid          = Bits(OUTPUT,4)
 126     val m_axi_araddr          = Bits(OUTPUT,32)
 127     //val m_axi_arregion      = Bits(OUTPUT,4)
 128     val m_axi_arlen           = Bits(OUTPUT,8)
 129     val m_axi_arsize          = Bits(OUTPUT,3)
 130     val m_axi_arburst         = Bits(OUTPUT,2)
 131     val m_axi_arlock          = Bits(OUTPUT,1)
 132     val m_axi_arcache         = Bits(OUTPUT,4)
 133     val m_axi_arprot          = Bits(OUTPUT,3)
 134     //val m_axi_arqos         = Bits(OUTPUT,4)
 135     val m_axi_arvalid         = Bool(OUTPUT)
 136     val m_axi_arready         = Bool(INPUT)
 137     //slave interface read data ports
 138     val m_axi_rready          = Bool(OUTPUT)
 139     //val m_axi_rid           = Bits(INPUT,4)
 140     val m_axi_rdata           = Bits(INPUT,64)
 141     val m_axi_rresp           = Bits(INPUT,2)
 142     val m_axi_rlast           = Bool(INPUT)
 143     val m_axi_rvalid          = Bool(INPUT)
 144
 145     //axi lite slave for control
 146     val s_axi_ctl_awaddr      = Bits(INPUT,32)
 147     val s_axi_ctl_awvalid     = Bool(INPUT)
 148     val s_axi_ctl_awready     = Bool(OUTPUT)
 149     val s_axi_ctl_wdata       = Bits(INPUT,32)
 150     val s_axi_ctl_wstrb       = Bits(INPUT,4)
 151     val s_axi_ctl_wvalid      = Bool(INPUT)
 152     val s_axi_ctl_wready      = Bool(OUTPUT)
 153     val s_axi_ctl_bresp       = Bits(OUTPUT,2)
 154     val s_axi_ctl_bvalid      = Bool(OUTPUT)
 155     val s_axi_ctl_bready      = Bool(INPUT)
 156     val s_axi_ctl_araddr      = Bits(INPUT,32)
 157     val s_axi_ctl_arvalid     = Bool(INPUT)
 158     val s_axi_ctl_arready     = Bool(OUTPUT)
 159     val s_axi_ctl_rdata       = Bits(OUTPUT,32)
 160     val s_axi_ctl_rresp       = Bits(OUTPUT,2)
 161     val s_axi_ctl_rvalid      = Bool(OUTPUT)
 162     val s_axi_ctl_rready      = Bool(INPUT)
 163  }
 164 }
 165 //scalastyle:off
 166
 167 //wrap vc707_axi_to_pcie_x1 black box in Nasti Bundles
 168
 169 class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
 170 {
 171   val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) {
 172     override def describe(resources: ResourceBindings): Description = {
 173       val Description(name, mapping) = super.describe(resources)
 174       val intc = "pcie_intc"
 175       def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
 176       def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x)
 177       val extra = Map(
 178         "#address-cells"     -> ofInt(3),
 179         "#size-cells"        -> ofInt(2),
 180         "#interrupt-cells"   -> ofInt(1),
 181         "device_type"        -> Seq(ResourceString("pci")),
 182         "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
 183         "interrupt-map"      -> Seq(1, 2, 3, 4).flatMap(ofMap),
 184         "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, perms)) =>
 185                                                                ResourceMapping(address, BigInt(0x02000000) << 64, perms) },
 186         "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
 187           "interrupt-controller" -> Nil,
 188           "#address-cells"       -> ofInt(0),
 189           "#interrupt-cells"     -> ofInt(1)))))
 190       Description(name, mapping ++ extra)
 191     }
 192   }
 193
 194   val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
 195     slaves = Seq(AXI4SlaveParameters(
 196       address       = List(AddressSet(0x60000000L, 0x1fffffffL)),
 197       resources     = Seq(Resource(device, "ranges")),
 198       executable    = true,
 199       supportsWrite = TransferSizes(1, 256),
 200       supportsRead  = TransferSizes(1, 256))),
 201     beatBytes = 8)))
 202
 203   val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
 204     slaves = Seq(AXI4SlaveParameters(
 205       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
 206       resources     = device.reg("control"),
 207       supportsWrite = TransferSizes(1, 4),
 208       supportsRead  = TransferSizes(1, 4),
 209       interleavedId = Some(0))), // AXI4-Lite never interleaves responses
 210     beatBytes = 4)))
 211
 212   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
 213     masters = Seq(AXI4MasterParameters(
 214       name    = "VC707 PCIe",
 215       id      = IdRange(0, 1),
 216       aligned = false)))))
 217
 218   val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 219
 220   lazy val module = new LazyModuleImp(this) {
 221     // The master on the control port must be AXI-lite
 222     require (control.edgesIn(0).master.endId == 1)
 223     // Must have exactly the right number of idBits
 224     require (slave.edgesIn(0).bundle.idBits == 4)
 225
 226     class VC707AXIToPCIeX1IOBundle extends Bundle with VC707AXIToPCIeX1IOSerial
 227                                                   with VC707AXIToPCIeX1IOClocksReset;
 228
 229     val io = new Bundle {
 230       val port = new VC707AXIToPCIeX1IOBundle
 231       val slave_in = slave.bundleIn
 232       val control_in = control.bundleIn
 233       val master_out = master.bundleOut
 234       val REFCLK = Bool(INPUT)
 235       val interrupt_out = intnode.bundleOut
 236     }
 237
 238     val blackbox = Module(new vc707axi_to_pcie_x1)
 239
 240     val s = io.slave_in(0)
 241     val c = io.control_in(0)
 242     val m = io.master_out(0)
 243
 244     //to top level
 245     blackbox.io.axi_aresetn         := io.port.axi_aresetn
 246     io.port.axi_aclk_out            := blackbox.io.axi_aclk_out
 247     io.port.axi_ctl_aclk_out        := blackbox.io.axi_ctl_aclk_out
 248     io.port.mmcm_lock               := blackbox.io.mmcm_lock
 249     io.port.pci_exp_txp             := blackbox.io.pci_exp_txp
 250     io.port.pci_exp_txn             := blackbox.io.pci_exp_txn
 251     blackbox.io.pci_exp_rxp         := io.port.pci_exp_rxp
 252     blackbox.io.pci_exp_rxn         := io.port.pci_exp_rxn
 253     io.interrupt_out(0)(0)          := blackbox.io.interrupt_out
 254     blackbox.io.REFCLK              := io.REFCLK
 255
 256     //s
 257     //AXI4 signals ordered as per AXI4 Specification (Release D) Section A.2
 258     //-{lock, cache, prot, qos}
 259     //-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
 260     //global signals
 261     //aclk                          :=
 262     //aresetn                       :=
 263     //slave interface write address
 264     blackbox.io.s_axi_awid          := s.aw.bits.id
 265     blackbox.io.s_axi_awaddr        := s.aw.bits.addr
 266     blackbox.io.s_axi_awlen         := s.aw.bits.len
 267     blackbox.io.s_axi_awsize        := s.aw.bits.size
 268     blackbox.io.s_axi_awburst       := s.aw.bits.burst
 269     //blackbox.io.s_axi_awlock      := s.aw.bits.lock
 270     //blackbox.io.s_axi_awcache     := s.aw.bits.cache
 271     //blackbox.io.s_axi_awprot      := s.aw.bits.prot
 272     //blackbox.io.s_axi_awqos       := s.aw.bits.qos
 273     blackbox.io.s_axi_awregion      := UInt(0)
 274     //blackbox.io.awuser            := s.aw.bits.user
 275     blackbox.io.s_axi_awvalid       := s.aw.valid
 276     s.aw.ready                   := blackbox.io.s_axi_awready
 277     //slave interface write data ports
 278     //blackbox.io.s_axi_wid         := s.w.bits.id
 279     blackbox.io.s_axi_wdata         := s.w.bits.data
 280     blackbox.io.s_axi_wstrb         := s.w.bits.strb
 281     blackbox.io.s_axi_wlast         := s.w.bits.last
 282     //blackbox.io.s_axi_wuser       := s.w.bits.user
 283     blackbox.io.s_axi_wvalid        := s.w.valid
 284     s.w.ready                    := blackbox.io.s_axi_wready
 285     //slave interface write response
 286     s.b.bits.id                  := blackbox.io.s_axi_bid
 287     s.b.bits.resp                := blackbox.io.s_axi_bresp
 288     //s.b.bits.user              := blackbox.io.s_axi_buser
 289     s.b.valid                    := blackbox.io.s_axi_bvalid
 290     blackbox.io.s_axi_bready        := s.b.ready
 291     //slave AXI interface read address ports
 292     blackbox.io.s_axi_arid          := s.ar.bits.id
 293     blackbox.io.s_axi_araddr        := s.ar.bits.addr
 294     blackbox.io.s_axi_arlen         := s.ar.bits.len
 295     blackbox.io.s_axi_arsize        := s.ar.bits.size
 296     blackbox.io.s_axi_arburst       := s.ar.bits.burst
 297     //blackbox.io.s_axi_arlock      := s.ar.bits.lock
 298     //blackbox.io.s_axi_arcache     := s.ar.bits.cache
 299     //blackbox.io.s_axi_arprot      := s.ar.bits.prot
 300     //blackbox.io.s_axi_arqos       := s.ar.bits.qos
 301     blackbox.io.s_axi_arregion      := UInt(0)
 302     //blackbox.io.s_axi_aruser      := s.ar.bits.user
 303     blackbox.io.s_axi_arvalid       := s.ar.valid
 304     s.ar.ready                   := blackbox.io.s_axi_arready
 305     //slave AXI interface read data ports
 306     s.r.bits.id                  := blackbox.io.s_axi_rid
 307     s.r.bits.data                := blackbox.io.s_axi_rdata
 308     s.r.bits.resp                := blackbox.io.s_axi_rresp
 309     s.r.bits.last                := blackbox.io.s_axi_rlast
 310     //s.r.bits.ruser             := blackbox.io.s_axi_ruser
 311     s.r.valid                    := blackbox.io.s_axi_rvalid
 312     blackbox.io.s_axi_rready        := s.r.ready
 313
 314     //ctl
 315     //axi-lite slave interface write address
 316     blackbox.io.s_axi_ctl_awaddr    := c.aw.bits.addr
 317     blackbox.io.s_axi_ctl_awvalid   := c.aw.valid
 318     c.aw.ready                 := blackbox.io.s_axi_ctl_awready
 319     //axi-lite slave interface write data ports
 320     blackbox.io.s_axi_ctl_wdata     := c.w.bits.data
 321     blackbox.io.s_axi_ctl_wstrb     := c.w.bits.strb
 322     blackbox.io.s_axi_ctl_wvalid    := c.w.valid
 323     c.w.ready                  := blackbox.io.s_axi_ctl_wready
 324     //axi-lite slave interface write response
 325     blackbox.io.s_axi_ctl_bready    := c.b.ready
 326     c.b.bits.id                := UInt(0)
 327     c.b.bits.resp              := blackbox.io.s_axi_ctl_bresp
 328     c.b.valid                  := blackbox.io.s_axi_ctl_bvalid
 329     //axi-lite slave AXI interface read address ports
 330     blackbox.io.s_axi_ctl_araddr    := c.ar.bits.addr
 331     blackbox.io.s_axi_ctl_arvalid   := c.ar.valid
 332     c.ar.ready                 := blackbox.io.s_axi_ctl_arready
 333     //slave AXI interface read data ports
 334     blackbox.io.s_axi_ctl_rready    := c.r.ready
 335     c.r.bits.id                := UInt(0)
 336     c.r.bits.data              := blackbox.io.s_axi_ctl_rdata
 337     c.r.bits.resp              := blackbox.io.s_axi_ctl_rresp
 338     c.r.bits.last              := Bool(true)
 339     c.r.valid                  := blackbox.io.s_axi_ctl_rvalid
 340
 341     //m
 342     //AXI4 signals ordered per AXI4 Specification (Release D) Section A.2
 343     //-{id,region,qos}
 344     //-{aclk, aresetn, awuser, wid, wuser, buser, ruser}
 345     //global signals
 346     //aclk                          :=
 347     //aresetn                       :=
 348     //master interface write address
 349     m.aw.bits.id                 := UInt(0)
 350     m.aw.bits.addr               := blackbox.io.m_axi_awaddr
 351     m.aw.bits.len                := blackbox.io.m_axi_awlen
 352     m.aw.bits.size               := blackbox.io.m_axi_awsize
 353     m.aw.bits.burst              := blackbox.io.m_axi_awburst
 354     m.aw.bits.lock               := blackbox.io.m_axi_awlock
 355     m.aw.bits.cache              := blackbox.io.m_axi_awcache
 356     m.aw.bits.prot               := blackbox.io.m_axi_awprot
 357     m.aw.bits.qos                := UInt(0)
 358     //m.aw.bits.region           := blackbox.io.m_axi_awregion
 359     //m.aw.bits.user             := blackbox.io.m_axi_awuser
 360     m.aw.valid                   := blackbox.io.m_axi_awvalid
 361     blackbox.io.m_axi_awready    := m.aw.ready
 362
 363     //master interface write data ports
 364     m.w.bits.data                := blackbox.io.m_axi_wdata
 365     m.w.bits.strb                := blackbox.io.m_axi_wstrb
 366     m.w.bits.last                := blackbox.io.m_axi_wlast
 367     //m.w.bits.user              := blackbox.io.m_axi_wuser
 368     m.w.valid                    := blackbox.io.m_axi_wvalid
 369     blackbox.io.m_axi_wready     := m.w.ready
 370
 371     //master interface write response
 372     //blackbox.io.m_axi_bid      := m.b.bits.id
 373     blackbox.io.m_axi_bresp      := m.b.bits.resp
 374     //blackbox.io.m_axi_buser    := m.b.bits.user
 375     blackbox.io.m_axi_bvalid     := m.b.valid
 376     m.b.ready                    := blackbox.io.m_axi_bready
 377
 378     //master AXI interface read address ports
 379     m.ar.bits.id                 := UInt(0)
 380     m.ar.bits.addr               := blackbox.io.m_axi_araddr
 381     m.ar.bits.len                := blackbox.io.m_axi_arlen
 382     m.ar.bits.size               := blackbox.io.m_axi_arsize
 383     m.ar.bits.burst              := blackbox.io.m_axi_arburst
 384     m.ar.bits.lock               := blackbox.io.m_axi_arlock
 385     m.ar.bits.cache              := blackbox.io.m_axi_arcache
 386     m.ar.bits.prot               := blackbox.io.m_axi_arprot
 387     m.ar.bits.qos                := UInt(0)
 388     //m.ar.bits.region           := blackbox.io.m_axi_arregion
 389     //m.ar.bits.user             := blackbox.io.s_axi_aruser
 390     m.ar.valid                   := blackbox.io.m_axi_arvalid
 391     blackbox.io.m_axi_arready    := m.ar.ready
 392
 393     //master AXI interface read data ports
 394     //blackbox.io.m_axi_rid      := m.r.bits.id
 395     blackbox.io.m_axi_rdata      := m.r.bits.data
 396     blackbox.io.m_axi_rresp      := m.r.bits.resp
 397     blackbox.io.m_axi_rlast      := m.r.bits.last
 398     //blackbox.io.s_axi_ruser    := s.bits.ruser
 399     blackbox.io.m_axi_rvalid     := m.r.valid
 400     m.r.ready                    := blackbox.io.m_axi_rready
 401   }
 402 }