src/main/scala/util/DeglitchShiftRegister.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5
   6 //Allows us to specify a different clock for a shift register
   7 // and to force input to be high for > 1 cycle.
   8 class DeglitchShiftRegister(shift: Int) extends Module {
   9   val io = new Bundle {
  10     val d = Bool(INPUT)
  11     val q = Bool(OUTPUT)
  12   }
  13   val sync = ShiftRegister(io.d, shift)
  14   val last = ShiftRegister(sync, 1)
  15   io.q := sync & last
  16 }
  17
  18 object DeglitchShiftRegister {
  19   def apply (shift: Int, d: Bool, clock: Clock,
  20     name: Option[String] = None): Bool = {
  21     val deglitch = Module (new DeglitchShiftRegister(shift))
  22     name.foreach(deglitch.suggestName(_))
  23     deglitch.clock := clock
  24     deglitch.reset := Bool(false)
  25     deglitch.io.d := d
  26     deglitch.io.q
  27   }
  28 }