1 // See LICENSE for license details.
2 package sifive.blocks.util
7 // MSB indicates full status
8 object NonBlockingEnqueue {
9 def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
10 val enqWidth = enq.bits.getWidth
12 require(regWidth > enqWidth)
16 RegWriteFn((valid, data) => {
21 RegField(regWidth - enqWidth - 1),
22 RegField.r(1, !enq.ready))
26 // MSB indicates empty status
27 object NonBlockingDequeue {
28 def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
29 val deqWidth = deq.bits.getWidth
31 require(regWidth > deqWidth)
36 (Bool(true), deq.bits)
38 RegField(regWidth - deqWidth - 1),
39 RegField.r(1, !deq.valid))