src/main/scala/util/ResetCatchAndSync.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5 import freechips.rocketchip.util.AsyncResetRegVec
   6
   7 /** Reset: asynchronous assert,
   8   *  synchronous de-assert
   9   *
  10   */
  11
  12 class ResetCatchAndSync (sync: Int = 3) extends Module {
  13
  14   val io = new Bundle {
  15     val sync_reset = Bool(OUTPUT)
  16   }
  17
  18   val reset_n_catch_reg = Module (new AsyncResetRegVec(sync, 0))
  19
  20   reset_n_catch_reg.io.en := Bool(true)
  21   reset_n_catch_reg.io.d  := Cat(Bool(true), reset_n_catch_reg.io.q >> 1)
  22
  23   io.sync_reset := ~reset_n_catch_reg.io.q(0)
  24
  25 }
  26
  27 object ResetCatchAndSync {
  28
  29   def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = {
  30
  31     val catcher = Module (new ResetCatchAndSync(sync))
  32     if (name.isDefined) {catcher.suggestName(name.get)}
  33     catcher.clock := clk
  34     catcher.reset := rst
  35
  36     catcher.io.sync_reset
  37   }
  38
  39   def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
  40   def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
  41
  42 }