src/main/scala/util/Timer.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5 import Chisel.ImplicitConversions._
   6 import regmapper._
   7 import util.WideCounter
   8
   9 class SlaveRegIF(w: Int) extends Bundle {
  10   val write = Valid(UInt(width = w)).flip
  11   val read = UInt(OUTPUT, w)
  12
  13   override def cloneType: this.type = new SlaveRegIF(w).asInstanceOf[this.type]
  14
  15   def toRegField(dummy: Int = 0): RegField = {
  16     def writeFn(valid: Bool, data: UInt): Bool = {
  17       write.valid := valid
  18       write.bits := data
  19       Bool(true)
  20     }
  21     RegField(w, RegReadFn(read), RegWriteFn((v, d) => writeFn(v, d)))
  22   }
  23 }
  24
  25
  26 abstract class GenericTimer extends Module {
  27   protected def countWidth: Int
  28   protected def cmpWidth: Int
  29   protected def ncmp: Int
  30   protected def countAlways: Bool
  31   protected def countEn: Bool
  32   protected def feed: Bool
  33   protected def ip: UInt
  34   protected def countAwake: Bool = Bool(false)
  35   protected def unlocked: Bool = Bool(true)
  36   protected def rsten: Bool = Bool(false)
  37   protected def deglitch: Bool = Bool(false)
  38   protected def sticky: Bool = Bool(false)
  39   protected def oneShot: Bool = Bool(false)
  40   protected def center: UInt = UInt(0)
  41   protected def gang: UInt = UInt(0)
  42   protected val scaleWidth = 4
  43   protected val regWidth = 32
  44   val maxcmp = 4
  45   require(ncmp <= maxcmp)
  46
  47   class GenericTimerIO extends Bundle {
  48     val regs = new Bundle {
  49       val cfg = new SlaveRegIF(regWidth)
  50       val countLo = new SlaveRegIF(regWidth)
  51       val countHi = new SlaveRegIF(regWidth)
  52       val s = new SlaveRegIF(cmpWidth)
  53       val cmp = Vec(ncmp, new SlaveRegIF(cmpWidth))
  54       val feed = new SlaveRegIF(regWidth)
  55       val key = new SlaveRegIF(regWidth)
  56     }
  57     val ip = Vec(ncmp, Bool()).asOutput
  58   }
  59
  60   def io: GenericTimerIO
  61
  62   protected val scale = RegEnable(io.regs.cfg.write.bits(scaleWidth-1, 0), io.regs.cfg.write.valid && unlocked)
  63   protected lazy val zerocmp = RegEnable(io.regs.cfg.write.bits(9), io.regs.cfg.write.valid && unlocked)
  64   protected val cmp = io.regs.cmp.map(c => RegEnable(c.write.bits, c.write.valid && unlocked))
  65
  66   protected val count = WideCounter(countWidth, countEn, reset = false)
  67   when (io.regs.countLo.write.valid && unlocked) { count := Cat(count >> regWidth, io.regs.countLo.write.bits) }
  68   if (countWidth > regWidth) when (io.regs.countHi.write.valid && unlocked) { count := Cat(io.regs.countHi.write.bits, count(regWidth-1, 0)) }
  69
  70   // generate periodic interrupt
  71   protected val s = (count >> scale)(cmpWidth-1, 0)
  72   // reset counter when fed or elapsed
  73   protected val elapsed =
  74     for (i <- 0 until ncmp)
  75       yield Mux(s(cmpWidth-1) && center(i), ~s, s) >= cmp(i)
  76   protected val countReset = feed || (zerocmp && elapsed(0))
  77   when (countReset) { count := 0 }
  78
  79   io.regs.cfg.read := Cat(ip, gang | UInt(0, maxcmp), UInt(0, maxcmp), center | UInt(0, maxcmp),
  80                           UInt(0, 2), countAwake || oneShot, countAlways, UInt(0, 1), deglitch, zerocmp, rsten || sticky, UInt(0, 8-scaleWidth), scale)
  81   io.regs.countLo.read := count
  82   io.regs.countHi.read := count >> regWidth
  83   io.regs.s.read := s
  84   (io.regs.cmp zip cmp) map { case (r, c) => r.read := c }
  85   io.regs.feed.read := 0
  86   io.regs.key.read := unlocked
  87   io.ip := io.ip.fromBits(ip)
  88 }
  89
  90
  91 object GenericTimer {
  92   def timerRegMap(t: GenericTimer, offset: Int, regBytes: Int): Seq[(Int, Seq[RegField])] = {
  93     val regs = Seq(
  94       0 -> t.io.regs.cfg,
  95       2 -> t.io.regs.countLo,
  96       3 -> t.io.regs.countHi,
  97       4 -> t.io.regs.s,
  98       6 -> t.io.regs.feed,
  99       7 -> t.io.regs.key)
 100     val cmpRegs = t.io.regs.cmp.zipWithIndex map { case (r, i) => (8 + i) -> r }
 101     for ((i, r) <- (regs ++ cmpRegs))
 102       yield (offset + regBytes*i) -> Seq(r.toRegField())
 103   }
 104 }