Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIO.scala

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index 12ac055bbb1d74ed224483129d39ba20e7ed2969..ae468cec2f909bb8511ea786092ef9ce7c484c7b 100644 (file)
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -2,10 +2,10 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
-import config.Parameters
-import regmapper._
-import uncore.tilelink2._
-import util.{AsyncResetRegVec, GenericParameterizedBundle}
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
 
 case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)