s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
val bitState = Reg(init = s_bit_idle)
- val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState === s_bit_idle) && stopCond && !bitCmdStop))
+ val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState =/= s_bit_idle) && stopCond && !bitCmdStop))
// bit FSM
when (arbLost) {
status.arbLost := false.B
}
status.transferInProgress := cmd.read || cmd.write
- status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
+ status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck // interrupt request flag is always generated
val statusReadReady = Reg(init = true.B)
- when (!statusReadReady) {
+ when (cmdAck || arbLost) { // => cmd.read or cmd.write deassert 1 cycle later => transferInProgress deassert 2 cycles later
+ statusReadReady := false.B // do not allow status read if status.transferInProgress is going to change
+ }
+ .elsewhen (!statusReadReady) {
statusReadReady := true.B
}