periphery: bus api update (#50)

[sifive-blocks.git] / src / main / scala / devices / pwm / PWMPins.scala

diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala
index 03acc902dad5bb77c5c872395c28f3f59695f095..aa7e032694d4aaf76ddf100a6264fbe86a2f8a30 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPins.scala
+++ b/src/main/scala/devices/pwm/PWMPins.scala
@@ -2,10 +2,6 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
-import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
-import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {