periphery: peripherals now in coreplex (#26)

[sifive-blocks.git] / src / main / scala / devices / uart / UART.scala

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 5732fd904b3df492f76e17dd1d4f6280708d5646..1a19be8eb03b94f68825d542c32ad69eb906562e 100644 (file)
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -2,8 +2,8 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import freechips.rocketchip.chip.RTCPeriod
 import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex.RTCPeriod
 import freechips.rocketchip.diplomacy.DTSTimebase
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
@@ -205,7 +205,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
   val rxm = Module(new UARTRx(params))
   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 
-  val divinit = p(DTSTimebase) * p(RTCPeriod) / 115200
+  val divinit = p(DTSTimebase) * BigInt(p(RTCPeriod).getOrElse(1)) / 115200
   val div = Reg(init = UInt(divinit, uartDivisorBits))
 
   private val stopCountBits = log2Up(uartStopBits)