Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1Periphery.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index 2a4389af53d02f2c83bacd93fcb80ae48d4782a2..008556a9a55d52d79c7caefe668be9ccdcebadda 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -2,9 +2,9 @@
 package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
-import diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2._
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink._
 
 trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks {
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)