X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707pciex1%2FXilinxVC707PCIeX1Periphery.scala;h=2a4389af53d02f2c83bacd93fcb80ae48d4782a2;hp=c994856f5b1c3b2cbffa87105cbc369323472e1a;hb=d4bb8a77ea7a0a9545dcaf93a4a2a32671c2dd47;hpb=79f64de12cac914c0c195dc876f34adcaf15f7d5

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index c994856..2a4389a 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -2,16 +2,11 @@
 package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksModule,
-  HasTopLevelNetworksBundle
-}
+import diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import rocketchip.HasSystemNetworks
 import uncore.tilelink2._
 
-trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
-
+trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks {
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
   private val intXing = LazyModule(new IntXing)
 
@@ -22,16 +17,20 @@ trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
   intXing.intnode := xilinxvc707pcie.intnode
 }
 
-trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
-  val xilinxvc707pcie = new XilinxVC707PCIeX1IO
+trait HasPeripheryXilinxVC707PCIeX1Bundle {
+  val xilinxvc707pcie: XilinxVC707PCIeX1IO
+  def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
+    pads <> xilinxvc707pcie
+  }
 }
 
-trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
+trait HasPeripheryXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
+    with HasPeripheryXilinxVC707PCIeX1Bundle {
   val outer: HasPeripheryXilinxVC707PCIeX1
-  val io: HasPeripheryXilinxVC707PCIeX1Bundle
+  val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
 
-  io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+  xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
 
   outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
-  outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
+  outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
 }