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(parent: 178ac84) | patch
xilinx mig: put a buffer infront of the controller (#13)
authorWesley W. Terpstra <wesley@sifive.com>
Thu, 11 May 2017 18:50:07 +0000 (11:50 -0700)
committerGitHub <noreply@github.com>
Thu, 11 May 2017 18:50:07 +0000 (11:50 -0700)
commitb3f960751234b26224a9e7f22f05ee73b83e2ca5
tree84ac88b74be14a7c4396fa428bfd9e5a77c1951etree
parent178ac84b59ebab63c182b821857f2b217cbbf17fcommit | diff
xilinx mig: put a buffer infront of the controller (#13)

This makes placement of the L2 and DDR controller easier.
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala diff | blob | history
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