Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

diff --cc src/main/scala/devices/gpio/GPIOPeriphery.scala
index cd658f17dd30625004f39fbfd49113d0e562c483,109ffb82991df1dcea50c16d013624b5f81373fb..d3b9cf5f17a49ba0c67aa54cdf27832f2267d158
--- 1/src/main/scala/devices/gpio/GPIOPeriphery.scala
--- 2/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@@ -10,12 -9,12 +9,12 @@@ import freechips.rocketchip.util.Hetero
  
  case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
  
- trait HasPeripheryGPIO extends HasSystemNetworks {
+ trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
    val gpioParams = p(PeripheryGPIOKey)
-   val gpios = gpioParams map {params =>
-     val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
-     gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     intBus.intnode := gpio.intnode
 -  val gpio = gpioParams map { params =>
++  val gpios = gpioParams map { params =>
+     val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
+     gpio.node := pbus.toVariableWidthSlaves
+     ibus.fromSync := gpio.intnode
      gpio
    }
  }

diff --cc src/main/scala/devices/i2c/I2CPeriphery.scala
Simple merge

diff --cc src/main/scala/devices/pwm/PWMPeriphery.scala
index f83cbafdfe9780ea83e865a8d94b65c4de9a8c4a,5ff9ccfe8f5b23dc17c79886c6afd2722a493070..ff5b6bbe1a20aff22e859e3a27c5b65f1ad0a430
--- 1/src/main/scala/devices/pwm/PWMPeriphery.scala
--- 2/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@@ -3,11 -3,10 +3,10 @@@ package sifive.blocks.devices.pw
  
  import Chisel._
  import freechips.rocketchip.config.Field
- import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
- import freechips.rocketchip.chip.HasSystemNetworks
- import freechips.rocketchip.tilelink.TLFragmenter
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+ import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
  import freechips.rocketchip.util.HeterogeneousBag
- import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 -import sifive.blocks.devices.gpio._
++import sifive.blocks.devices.pinctrl.{Pin}
  
  class PWMPortIO(val c: PWMParams) extends Bundle {
    val port = Vec(c.ncmp, Bool()).asOutput

diff --cc src/main/scala/devices/spi/SPIPeriphery.scala
index f2b3b4198fc1e7ce96b02d612581c38f5d5dca2e,37151bd06cda84a0e8a5f6b9178824418c024e64..80978946103eec972449e71d82227beceb2b3e86
--- 1/src/main/scala/devices/spi/SPIPeriphery.scala
--- 2/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@@ -36,13 -41,13 +36,13 @@@ trait HasPeripherySPIModuleImp extends 
  
  case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
  
- trait HasPeripherySPIFlash extends HasSystemNetworks {
+ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
    val spiFlashParams = p(PeripherySPIFlashKey)  
 -  val qspi = spiFlashParams map { params =>
 +  val qspis = spiFlashParams map { params =>
-     val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
-     qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-     qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
-     intBus.intnode := qspi.intnode
+     val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+     qspi.rnode := pbus.toVariableWidthSlaves
+     qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
+     ibus.fromSync := qspi.intnode
      qspi
    }
  }

diff --cc src/main/scala/devices/uart/UARTPeriphery.scala
index 105592d2042e7a6f19d265d37c45f3e5ff771c46,c925a38a0e47307e281788a7e30abb195ab8eb27..d42850f88eca4388a571ac86e47743c69406beef
--- 1/src/main/scala/devices/uart/UARTPeriphery.scala
--- 2/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@@ -2,12 -2,10 +2,11 @@@
  package sifive.blocks.devices.uart
  
  import Chisel._
 +import chisel3.experimental.{withClockAndReset}
  import freechips.rocketchip.config.Field
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
  import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
- import freechips.rocketchip.chip.HasSystemNetworks
- import freechips.rocketchip.tilelink.TLFragmenter
- import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 -import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
++import sifive.blocks.devices.pinctrl.{Pin}
  import sifive.blocks.util.ShiftRegisterInit
  
  case object PeripheryUARTKey extends Field[Seq[UARTParams]]