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i2c: Allow irq to be cleared
author
Megan Wachs
<megan@sifive.com>
Fri, 16 Feb 2018 23:49:09 +0000
(15:49 -0800)
committer
Megan Wachs
<megan@sifive.com>
Sat, 17 Feb 2018 00:34:10 +0000
(16:34 -0800)
src/main/scala/devices/i2c/I2C.scala
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diff --git
a/src/main/scala/devices/i2c/I2C.scala
b/src/main/scala/devices/i2c/I2C.scala
index aecf2dca476cde9bb5bfb94adbb650ed988b0959..d767a265f05c5add29c63ef0e53e70bc96ba08c7 100644
(file)
--- a/
src/main/scala/devices/i2c/I2C.scala
+++ b/
src/main/scala/devices/i2c/I2C.scala
@@
-488,16
+488,16
@@
trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
// hack: b/c the same register offset is used to write cmd and read status
val nextCmd = Wire(UInt(8.W))
// hack: b/c the same register offset is used to write cmd and read status
val nextCmd = Wire(UInt(8.W))
- nextCmd := cmd.asUInt
cmd := (new CommandBundle).fromBits(nextCmd)
cmd := (new CommandBundle).fromBits(nextCmd)
+ nextCmd := cmd.asUInt & 0xFE.U // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below)
+ // Note: This wins over the regmap update of nextCmd (even if something tries to write them to 1, these values take priority).
when (cmdAck || arbLost) {
cmd.start := false.B // clear command bits when done
cmd.stop := false.B // or when aribitration lost
cmd.read := false.B
cmd.write := false.B
}
when (cmdAck || arbLost) {
cmd.start := false.B // clear command bits when done
cmd.stop := false.B // or when aribitration lost
cmd.read := false.B
cmd.write := false.B
}
- cmd.irqAck := false.B // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below)
status.receivedAck := receivedAck
when (stopCond) {
status.receivedAck := receivedAck
when (stopCond) {