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Do not allow status read if status.transferInProgress is going to change next cycle
i2c_int
author
Alex Solomatnikov
<sols@sifive.com>
Fri, 23 Feb 2018 02:43:39 +0000
(18:43 -0800)
committer
Alex Solomatnikov
<sols@sifive.com>
Fri, 23 Feb 2018 02:43:39 +0000
(18:43 -0800)
src/main/scala/devices/i2c/I2C.scala
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diff --git
a/src/main/scala/devices/i2c/I2C.scala
b/src/main/scala/devices/i2c/I2C.scala
index d767a265f05c5add29c63ef0e53e70bc96ba08c7..be7ff4a06a066f33491c47555d2ffd6c5afea86a 100644
(file)
--- a/
src/main/scala/devices/i2c/I2C.scala
+++ b/
src/main/scala/devices/i2c/I2C.scala
@@
-514,11
+514,14
@@
trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
status.arbLost := false.B
}
status.transferInProgress := cmd.read || cmd.write
status.arbLost := false.B
}
status.transferInProgress := cmd.read || cmd.write
- status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
+ status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
// interrupt request flag is always generated
val statusReadReady = Reg(init = true.B)
val statusReadReady = Reg(init = true.B)
- when (!statusReadReady) {
+ when (cmdAck || arbLost) { // => cmd.read or cmd.write deassert 1 cycle later => transferInProgress deassert 2 cycles later
+ statusReadReady := false.B // do not allow status read if status.transferInProgress is going to change
+ }
+ .elsewhen (!statusReadReady) {
statusReadReady := true.B
}
statusReadReady := true.B
}