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periphery: peripherals now in coreplex (#26)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
xilinxvc707mig
/
XilinxVC707MIG.scala
2017-07-23
Henry Cook
periphery: peripherals now in coreplex (#26)
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2017-07-07
Henry Cook
Refactor package hierarchy. (#25)
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2017-06-30
Wesley W. Terpstra
vc707 axi enhancements (#24)
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2017-06-29
Wesley W. Terpstra
mig: fix MemoryDevice to use 'reg' properly
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2017-06-29
Wesley W. Terpstra
diplomacy: add reg-names to devices (#22)
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2017-05-13
Wesley W. Terpstra
Merge pull request #14 from sifive/async-pcie
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2017-05-13
Wesley W. Terpstra
vc707mig: use an external ibuf
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2017-05-11
Wesley W. Terpstra
xilinx mig: put a buffer infront of the controller...
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2017-05-03
Henry Cook
Merge pull request #10 from sifive/axi-mmio
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2017-04-26
Wesley W. Terpstra
axi4: switch to new pipelined converters
axi-mmio
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2017-04-25
Henry Styles
Merge pull request #9 from sifive/vc707_mig_analog_inout
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2017-04-25
Henry Styles
Use _chisel3 analog for MIG inout
vc707_mig_analog_inout
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2017-03-10
Megan Wachs
Merge remote-tracking branch 'origin/master' into debug...
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2017-03-03
Wesley W. Terpstra
Merge pull request #4 from sifive/periphery-keys
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2017-03-03
Wesley W. Terpstra
devices: include DTS meta-data
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2017-01-20
Wesley W. Terpstra
mig: track change to Blind port API in rocket
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2016-11-29
SiFive
Initial commit.
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