2018-03-04 Henry Cookspi: SPIParamsBase param needs to be public master
2018-03-04 Jack KoenigRemove cloneTypes in favor of autoclonetype (#51)
2018-03-01 Henry Cookperiphery: bus api update (#50)
2018-02-23 solomatnikovBug fix: arbLost should be asserted when bitState ...
2018-02-23 solomatnikovMerge pull request #48 from sifive/i2c_int
2018-02-23 Alex SolomatnikovDo not allow status read if status.transferInProgress... i2c_int
2018-02-17 Megan Wachsi2c: Allow irq to be cleared
2018-01-05 Albert Ouuart: Eliminate systemic baud rate error with low divis...
2017-11-09 Megan WachsMerge pull request #46 from sifive/gpio_iof_pueds
2017-11-08 Megan WachsGPIO: IOF should not override PUE and DS gpio_iof_pueds
2017-11-02 Wesley W. TerpstraPMU: adapt to new chisel API (#45)
2017-10-28 Wesley W. Terpstradevices: switch to using node-style API (#44)
2017-10-26 Wesley W. Terpstrasifive-blocks: update to new rocket API (#43)
2017-10-11 Megan WachsMerge pull request #42 from sifive/enhanced_to_base_pin
2017-10-06 Megan Wachspinctrl: Add the ability to convert EnhancedPin to... enhanced_to_base_pin
2017-10-05 Megan WachsMerge pull request #41 from sifive/pwm_invert
2017-10-02 Megan WachsPWM: Add the ability to invert the output directly... pwm_invert
2017-09-27 Wesley W. Terpstradiplomacy: update to new API (#40)
2017-09-25 Megan WachsMerge pull request #39 from sifive/signal_bundles
2017-09-22 Megan WachsGPIO Pins needs clone type. signal_bundles
2017-09-22 Megan Wachssignal_bundles: add missing file
2017-09-22 Megan Wachspinctrl: Create extendable Signal classes
2017-09-20 Megan Wachsdevice pins: Create classes that can be something other...
2017-09-20 Megan WachsSPI: Make it easier to build arbitrary bundles
2017-09-15 Henry Cookuart: use PeripheryBusKey (#38)
2017-09-07 Megan WachsMerge pull request #37 from sifive/synchronizers
2017-09-06 Megan Wachsshiftregs: Use SyncResetSynchronizerShiftReg primitives... synchronizers
2017-09-06 Megan Wachsi2c/uart: Name the synchronizers
2017-09-06 Megan Wachsgpio: Use Synchronizer for the inputs
2017-09-06 Megan Wachsi2c, uart: Use Synchronizer primitives for the inputs
2017-09-06 Megan WachsShiftRegInit: use the rocket-chip version since it...
2017-09-06 Megan Wachsregs: remove duplicate ShiftReg file which is now in...
2017-08-25 Megan Wachsremove duplicate ResetCatchAndSync definition
2017-08-20 Megan WachsMerge pull request #35 from sifive/spi-buffers
2017-08-20 Megan Wachsspi: Make memory mapped interface depth a parameter
2017-08-19 Wesley W. Terpstraspi: put a request buffer infront of SPI
2017-08-18 Shreesha SrinathMerge pull request #34 from ss2783/master
2017-08-18 Shreesha SrinathRenamed ShiftReg to ShiftRegister
2017-08-18 Shreesha SrinathUpdates to go with the fpga-shells directory
2017-08-10 Wesley W. Terpstrauart: make it easy to simulate large text printouts...
2017-08-04 Shreesha SrinathMerge pull request #31 from ss2783/fix-mockaon
2017-08-03 Shreesha Srinathmockaon: Adds logic to detect external rtc toggles
2017-08-02 Albert OuMerge pull request #30 from sifive/spi
2017-08-02 Albert Ouspi: Fix invalid D channel response when flash interfac...
2017-08-02 Henry Cookallow bundle content params to be specified via a def...
2017-07-26 Wesley W. Terpstraspi: remove removed sink arg
2017-07-25 Yunsup LeeMerge pull request #27 from sifive/typed_pad_ctrl
2017-07-25 Yunsup Leemockaon: rename pads to pins
2017-07-25 Megan WachsPorts: Rename the 'fromXYZPort' to 'fromPort' since...
2017-07-25 Megan WachsMerge remote-tracking branch 'origin/master' into typed...
2017-07-25 Yunsup Leeuart: use PeripheryBusParams.frequency to calculate...
2017-07-24 Megan WachsMerge remote-tracking branch 'origin/master' into typed...
2017-07-23 Henry Cookperiphery: peripherals now in coreplex (#26)
2017-07-20 Megan Wachsgpio: Add missing file
2017-07-20 Megan WachsAdd missing cloneType methods to pin bundles
2017-07-20 Megan Wachsi2c: Remove pluralization on the bundle name, i2c not...
2017-07-19 Megan WachsRemove pluralization on interface names. Require clocks...
2017-07-19 Megan WachsMake it possible to adjust the type of pad controls...
2017-07-07 Henry CookRefactor package hierarchy. (#25)
2017-06-30 Wesley W. Terpstravc707 axi enhancements (#24)
2017-06-29 Wesley W. Terpstramig: fix MemoryDevice to use 'reg' properly
2017-06-29 Wesley W. Terpstraspi: include mem region (#23)
2017-06-29 Wesley W. Terpstradiplomacy: add reg-names to devices (#22)
2017-06-19 Megan Wachsgpio: Make IOF optional (#21)
2017-06-15 Henry Cookmake some base bundle classes easier to clone (#20)
2017-06-15 Wesley W. Terpstraspi: add dts ranges field for memory mapped spi (#19)
2017-06-13 Henry CookMerge pull request #18 from sifive/lazy-raw-module-imp
2017-06-13 Megan WachsMore Peripheral-to-pins cleanups
2017-06-13 Megan WachsUART: actually return the pins, not just the module...
2017-06-13 Megan WachsGPIO/SPI/I2C: Add sync stages in place of dummy variabl...
2017-06-13 Megan WachsGPIO/SPI/I2C: Add sync stages in place of dummy variabl...
2017-06-12 Henry Cookperiphery: convert periphery bundle traits to work...
2017-06-10 Megan WachsMerge pull request #17 from sifive/peripheral_options
2017-06-09 Megan Wachsperipheral_options: Actually compiles
2017-06-08 Megan WachsSPIFlash: make it listable
2017-06-08 Megan WachsGPIO: Make GPIO peripheral another listable one
2017-06-02 Wesley W. Terpstravc707axi: track rocketchip API changes (#16)
2017-05-14 Wesley W. Terpstrauart: power-on with the right divider for the design...
2017-05-13 Wesley W. TerpstraMerge pull request #14 from sifive/async-pcie
2017-05-13 Wesley W. Terpstravc707mig: use an external ibuf
2017-05-13 Wesley W. Terpstraxilinxvc707pciex1: push to a dedicated clock domain
2017-05-11 Wesley W. Terpstraxilinx mig: put a buffer infront of the controller...
2017-05-08 Wesley W. Terpstraxilinxvc707pciex1: better wrapper for AXI4-Lite control...
2017-05-03 Henry CookMerge pull request #10 from sifive/axi-mmio
2017-05-02 Yunsup LeeMerge pull request #11 from sifive/spi
2017-05-02 Albert Ouspi: Fix off-by-one error in calculating cycles per...
2017-05-02 Albert Ouspi: Fix io.port.dq(3) output enable
2017-04-26 Wesley W. Terpstraaxi4: switch to new pipelined converters axi-mmio
2017-04-25 Henry StylesMerge pull request #9 from sifive/vc707_mig_analog_inout
2017-04-25 Henry StylesUse _chisel3 analog for MIG inout vc707_mig_analog_inout
2017-04-25 solomatnikovAdded stall for read after write (#8)
2017-04-10 Megan WachsMerge pull request #7 from sifive/ndreset
2017-04-07 Megan WachsMockAON: Accept the non-debug interrupt as an input...
2017-03-31 Megan WachsMerge pull request #6 from sifive/debug_v013
2017-03-31 Megan Wachsspi: correct polarity of FIRRTL combo loop detection...
2017-03-31 Megan WachsMerge remote-tracking branch 'origin/fix-false-comb...
2017-03-31 Jack Koenig"Fix" false combinational loop through SPIArbiter fix-false-comb-loop
2017-03-28 Megan WachsMerge remote-tracking branch 'origin/master' into debug...
2017-03-26 Yunsup Leerename l2FrontendBus as fsb
2017-03-25 Yunsup Leerename l2FrontendBus as fsb