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use git submodule soclayout for source files, rather than
[soc-cocotb-sim.git]
/
ls180
/
pll.v
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// PLL simulation model; just connect input clock to output clock
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module pll(ref_v, div_out_test, a0, a1, vco_test_ana, out_v);
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input a0;
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input a1;
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output div_out_test;
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output out_v;
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input ref_v;
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output vco_test_ana;
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assign out_v = ref_v;
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assign vco_test_ana = 0;
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assign div_out_test = 0;
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endmodule
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