ls180/post_pnr/Makefile

   1 .PHONY: all chip prepare cocotb gitupdate
   2
   3 all: prepare cocotb
   4
   5 # submodule update
   6 gitupdate:
   7         git submodule update --init --remote
   8
   9 # gets the nsxlib and niolib files, and munges the contents of vst_src
  10 prepare:
  11         ./vbe2vst.py
  12         ./vst_correct.py
  13
  14 # runs cocotb test
  15 cocotb:
  16         (cd cocotb && ./run_ghdl.sh)
  17
  18 # builds just for fun (double-check) ghdl works
  19 chip:
  20         ./vhd2obj.py
  21         (cd obj && ghdl -e -g --std=08 chip)
  22         (cd obj && ghdl -r -g --std=08 chip)
  23
  24 # imports all ghdl "stuff" and outputs verilog
  25 chip_v: chip
  26         (cd obj && yosys -m ghdl -p 'ghdl --std=08 chip' \
  27          -p 'proc' -p 'write_verilog chip.v')