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[soc-cocotb-sim.git] / ls180 / post_pnr / chip_corona / chip_r.vhd
1 LIBRARY IEEE;
2 USE IEEE.std_logic_1164.ALL;
3 USE IEEE.numeric_std.ALL;
4
5 -- =======================================================================
6 -- Coriolis Structural VHDL Driver
7 -- Generated on Apr 10, 2021, 14:21
8 --
9 -- To be interoperable with Alliance, it uses it's special VHDL subset.
10 -- ("man vhdl" under Alliance for more informations)
11 -- =======================================================================
12
13 entity chip_r is
14 port ( eint_0 : inout std_logic
15 ; eint_1 : inout std_logic
16 ; eint_2 : inout std_logic
17 ; gpio_10 : inout std_logic
18 ; gpio_11 : inout std_logic
19 ; gpio_12 : inout std_logic
20 ; gpio_13 : inout std_logic
21 ; gpio_14 : inout std_logic
22 ; gpio_15 : inout std_logic
23 ; i2c_sda : inout std_logic
24 ; jtag_tck : inout std_logic
25 ; jtag_tdi : inout std_logic
26 ; jtag_tms : inout std_logic
27 ; sdram_dq_10 : inout std_logic
28 ; sdram_dq_11 : inout std_logic
29 ; sdram_dq_12 : inout std_logic
30 ; sdram_dq_13 : inout std_logic
31 ; sdram_dq_14 : inout std_logic
32 ; sdram_dq_15 : inout std_logic
33 ; spimaster_miso : inout std_logic
34 ; sys_clk : inout std_logic
35 ; sys_rst : inout std_logic
36 ; uart_rx : inout std_logic
37 ; uart_tx : inout std_logic
38 ; nc : inout std_logic_vector(39 downto 0)
39 ; gpio_0 : inout std_logic
40 ; gpio_1 : inout std_logic
41 ; gpio_2 : inout std_logic
42 ; gpio_3 : inout std_logic
43 ; gpio_4 : inout std_logic
44 ; gpio_5 : inout std_logic
45 ; gpio_6 : inout std_logic
46 ; gpio_7 : inout std_logic
47 ; gpio_8 : inout std_logic
48 ; gpio_9 : inout std_logic
49 ; i2c_scl : inout std_logic
50 ; jtag_tdo : inout std_logic
51 ; sdram_cas_n : inout std_logic
52 ; sdram_cke : inout std_logic
53 ; sdram_clock : inout std_logic
54 ; sdram_cs_n : inout std_logic
55 ; sdram_dq_0 : inout std_logic
56 ; sdram_dq_1 : inout std_logic
57 ; sdram_dq_2 : inout std_logic
58 ; sdram_dq_3 : inout std_logic
59 ; sdram_dq_4 : inout std_logic
60 ; sdram_dq_5 : inout std_logic
61 ; sdram_dq_6 : inout std_logic
62 ; sdram_dq_7 : inout std_logic
63 ; sdram_dq_8 : inout std_logic
64 ; sdram_dq_9 : inout std_logic
65 ; sdram_ras_n : inout std_logic
66 ; sdram_we_n : inout std_logic
67 ; spimaster_clk : inout std_logic
68 ; spimaster_cs_n : inout std_logic
69 ; spimaster_mosi : inout std_logic
70 ; sdram_ba : out std_logic_vector(1 downto 0)
71 ; sdram_dm : out std_logic_vector(1 downto 0)
72 ; sdram_a : out std_logic_vector(12 downto 0)
73 ; iovdd : in bit
74 ; iovss : in bit
75 ; vdd : in bit
76 ; vss : in bit
77 );
78 end chip_r;
79
80 architecture structural of chip_r is
81
82 component corona_cts_r
83 port ( eint_0_from_pad : in bit
84 ; eint_1_from_pad : in bit
85 ; eint_2_from_pad : in bit
86 ; i2c_sda_i_from_pad : in bit
87 ; jtag_tck_from_pad : in bit
88 ; jtag_tdi_from_pad : in bit
89 ; jtag_tms_from_pad : in bit
90 ; spimaster_miso_from_pad : in bit
91 ; sys_clk_from_pad : in bit
92 ; sys_rst_from_pad : in bit
93 ; uart_rx_from_pad : in bit
94 ; uart_tx_from_pad : in bit
95 ; gpio_i_from_pad : in bit_vector(15 downto 0)
96 ; sdram_dq_i_from_pad : in bit_vector(15 downto 0)
97 ; nc_from_pad : in bit_vector(39 downto 0)
98 ; eint_0_enable_to_pad : out bit
99 ; eint_1_enable_to_pad : out bit
100 ; eint_2_enable_to_pad : out bit
101 ; i2c_scl_enable_to_pad : out bit
102 ; i2c_scl_to_pad : out bit
103 ; i2c_sda_o_to_pad : out bit
104 ; i2c_sda_oe_to_pad : out bit
105 ; jtag_tck_enable_to_pad : out bit
106 ; jtag_tdi_enable_to_pad : out bit
107 ; jtag_tdo_enable_to_pad : out bit
108 ; jtag_tdo_to_pad : out bit
109 ; jtag_tms_enable_to_pad : out bit
110 ; nc_0_enable_to_pad : out bit
111 ; nc_10_enable_to_pad : out bit
112 ; nc_11_enable_to_pad : out bit
113 ; nc_12_enable_to_pad : out bit
114 ; nc_13_enable_to_pad : out bit
115 ; nc_14_enable_to_pad : out bit
116 ; nc_15_enable_to_pad : out bit
117 ; nc_16_enable_to_pad : out bit
118 ; nc_17_enable_to_pad : out bit
119 ; nc_18_enable_to_pad : out bit
120 ; nc_19_enable_to_pad : out bit
121 ; nc_1_enable_to_pad : out bit
122 ; nc_20_enable_to_pad : out bit
123 ; nc_21_enable_to_pad : out bit
124 ; nc_22_enable_to_pad : out bit
125 ; nc_23_enable_to_pad : out bit
126 ; nc_24_enable_to_pad : out bit
127 ; nc_25_enable_to_pad : out bit
128 ; nc_26_enable_to_pad : out bit
129 ; nc_27_enable_to_pad : out bit
130 ; nc_28_enable_to_pad : out bit
131 ; nc_29_enable_to_pad : out bit
132 ; nc_2_enable_to_pad : out bit
133 ; nc_30_enable_to_pad : out bit
134 ; nc_31_enable_to_pad : out bit
135 ; nc_32_enable_to_pad : out bit
136 ; nc_33_enable_to_pad : out bit
137 ; nc_34_enable_to_pad : out bit
138 ; nc_35_enable_to_pad : out bit
139 ; nc_36_enable_to_pad : out bit
140 ; nc_37_enable_to_pad : out bit
141 ; nc_38_enable_to_pad : out bit
142 ; nc_39_enable_to_pad : out bit
143 ; nc_3_enable_to_pad : out bit
144 ; nc_4_enable_to_pad : out bit
145 ; nc_5_enable_to_pad : out bit
146 ; nc_6_enable_to_pad : out bit
147 ; nc_7_enable_to_pad : out bit
148 ; nc_8_enable_to_pad : out bit
149 ; nc_9_enable_to_pad : out bit
150 ; sdram_a_0_enable_to_pad : out bit
151 ; sdram_a_10_enable_to_pad : out bit
152 ; sdram_a_11_enable_to_pad : out bit
153 ; sdram_a_12_enable_to_pad : out bit
154 ; sdram_a_1_enable_to_pad : out bit
155 ; sdram_a_2_enable_to_pad : out bit
156 ; sdram_a_3_enable_to_pad : out bit
157 ; sdram_a_4_enable_to_pad : out bit
158 ; sdram_a_5_enable_to_pad : out bit
159 ; sdram_a_6_enable_to_pad : out bit
160 ; sdram_a_7_enable_to_pad : out bit
161 ; sdram_a_8_enable_to_pad : out bit
162 ; sdram_a_9_enable_to_pad : out bit
163 ; sdram_ba_0_enable_to_pad : out bit
164 ; sdram_ba_1_enable_to_pad : out bit
165 ; sdram_cas_n_enable_to_pad : out bit
166 ; sdram_cas_n_to_pad : out bit
167 ; sdram_cke_enable_to_pad : out bit
168 ; sdram_cke_to_pad : out bit
169 ; sdram_clock_enable_to_pad : out bit
170 ; sdram_clock_to_pad : out bit
171 ; sdram_cs_n_enable_to_pad : out bit
172 ; sdram_cs_n_to_pad : out bit
173 ; sdram_dm_0_enable_to_pad : out bit
174 ; sdram_dm_1_enable_to_pad : out bit
175 ; sdram_ras_n_enable_to_pad : out bit
176 ; sdram_ras_n_to_pad : out bit
177 ; sdram_we_n_enable_to_pad : out bit
178 ; sdram_we_n_to_pad : out bit
179 ; spimaster_clk_enable_to_pad : out bit
180 ; spimaster_clk_to_pad : out bit
181 ; spimaster_cs_n_enable_to_pad : out bit
182 ; spimaster_cs_n_to_pad : out bit
183 ; spimaster_miso_enable_to_pad : out bit
184 ; spimaster_mosi_enable_to_pad : out bit
185 ; spimaster_mosi_to_pad : out bit
186 ; sys_clk_enable_to_pad : out bit
187 ; sys_rst_enable_to_pad : out bit
188 ; uart_rx_enable_to_pad : out bit
189 ; uart_tx_enable_to_pad : out bit
190 ; sdram_ba_to_pad : out bit_vector(1 downto 0)
191 ; sdram_dm_to_pad : out bit_vector(1 downto 0)
192 ; sdram_a_to_pad : out bit_vector(12 downto 0)
193 ; gpio_o_to_pad : out bit_vector(15 downto 0)
194 ; gpio_oe_to_pad : out bit_vector(15 downto 0)
195 ; sdram_dq_o_to_pad : out bit_vector(15 downto 0)
196 ; sdram_dq_oe_to_pad : out bit_vector(15 downto 0)
197 ; vdd : in bit
198 ; vss : in bit
199 );
200 end component;
201
202 component cmpt_iovss
203 port ( iovdd : in bit
204 ; iovss : in bit
205 ; vdd : in bit
206 ; vss : in bit
207 );
208 end component;
209
210 component cmpt_iovdd
211 port ( iovdd : in bit
212 ; iovss : in bit
213 ; vdd : in bit
214 ; vss : in bit
215 );
216 end component;
217
218 component cmpt_vss
219 port ( iovdd : in bit
220 ; iovss : in bit
221 ; vdd : in bit
222 ; vss : in bit
223 );
224 end component;
225
226 component cmpt_vdd
227 port ( iovdd : in bit
228 ; iovss : in bit
229 ; vdd : in bit
230 ; vss : in bit
231 );
232 end component;
233
234 component cmpt_gpio
235 port ( i : in bit
236 ; oe : in bit
237 ; o : out bit
238 ; pad : inout std_logic
239 ; iovdd : in bit
240 ; iovss : in bit
241 ; vdd : in bit
242 ; vss : in bit
243 );
244 end component;
245
246 signal chip_dummy_0 : bit;
247 signal chip_dummy_1 : bit;
248 signal chip_dummy_10 : bit;
249 signal chip_dummy_11 : bit;
250 signal chip_dummy_12 : bit;
251 signal chip_dummy_13 : bit;
252 signal chip_dummy_14 : bit;
253 signal chip_dummy_15 : bit;
254 signal chip_dummy_16 : bit;
255 signal chip_dummy_17 : bit;
256 signal chip_dummy_18 : bit;
257 signal chip_dummy_19 : bit;
258 signal chip_dummy_2 : bit;
259 signal chip_dummy_20 : bit;
260 signal chip_dummy_21 : bit;
261 signal chip_dummy_22 : bit;
262 signal chip_dummy_23 : bit;
263 signal chip_dummy_24 : bit;
264 signal chip_dummy_25 : bit;
265 signal chip_dummy_26 : bit;
266 signal chip_dummy_27 : bit;
267 signal chip_dummy_28 : bit;
268 signal chip_dummy_29 : bit;
269 signal chip_dummy_3 : bit;
270 signal chip_dummy_30 : bit;
271 signal chip_dummy_31 : bit;
272 signal chip_dummy_32 : bit;
273 signal chip_dummy_33 : bit;
274 signal chip_dummy_34 : bit;
275 signal chip_dummy_35 : bit;
276 signal chip_dummy_36 : bit;
277 signal chip_dummy_37 : bit;
278 signal chip_dummy_38 : bit;
279 signal chip_dummy_39 : bit;
280 signal chip_dummy_4 : bit;
281 signal chip_dummy_40 : bit;
282 signal chip_dummy_41 : bit;
283 signal chip_dummy_42 : bit;
284 signal chip_dummy_43 : bit;
285 signal chip_dummy_44 : bit;
286 signal chip_dummy_45 : bit;
287 signal chip_dummy_46 : bit;
288 signal chip_dummy_47 : bit;
289 signal chip_dummy_48 : bit;
290 signal chip_dummy_49 : bit;
291 signal chip_dummy_5 : bit;
292 signal chip_dummy_50 : bit;
293 signal chip_dummy_51 : bit;
294 signal chip_dummy_52 : bit;
295 signal chip_dummy_53 : bit;
296 signal chip_dummy_54 : bit;
297 signal chip_dummy_55 : bit;
298 signal chip_dummy_56 : bit;
299 signal chip_dummy_57 : bit;
300 signal chip_dummy_58 : bit;
301 signal chip_dummy_59 : bit;
302 signal chip_dummy_6 : bit;
303 signal chip_dummy_60 : bit;
304 signal chip_dummy_61 : bit;
305 signal chip_dummy_62 : bit;
306 signal chip_dummy_63 : bit;
307 signal chip_dummy_64 : bit;
308 signal chip_dummy_65 : bit;
309 signal chip_dummy_66 : bit;
310 signal chip_dummy_67 : bit;
311 signal chip_dummy_68 : bit;
312 signal chip_dummy_69 : bit;
313 signal chip_dummy_7 : bit;
314 signal chip_dummy_70 : bit;
315 signal chip_dummy_71 : bit;
316 signal chip_dummy_72 : bit;
317 signal chip_dummy_73 : bit;
318 signal chip_dummy_74 : bit;
319 signal chip_dummy_75 : bit;
320 signal chip_dummy_76 : bit;
321 signal chip_dummy_77 : bit;
322 signal chip_dummy_78 : bit;
323 signal chip_dummy_8 : bit;
324 signal chip_dummy_9 : bit;
325 signal eint_0_enable_to_pad : bit;
326 signal eint_0_from_pad : bit;
327 signal eint_1_enable_to_pad : bit;
328 signal eint_1_from_pad : bit;
329 signal eint_2_enable_to_pad : bit;
330 signal eint_2_from_pad : bit;
331 signal i2c_scl_enable_to_pad : bit;
332 signal i2c_scl_to_pad : bit;
333 signal i2c_sda_i_from_pad : bit;
334 signal i2c_sda_o_to_pad : bit;
335 signal i2c_sda_oe_to_pad : bit;
336 signal jtag_tck_enable_to_pad : bit;
337 signal jtag_tck_from_pad : bit;
338 signal jtag_tdi_enable_to_pad : bit;
339 signal jtag_tdi_from_pad : bit;
340 signal jtag_tdo_enable_to_pad : bit;
341 signal jtag_tdo_to_pad : bit;
342 signal jtag_tms_enable_to_pad : bit;
343 signal jtag_tms_from_pad : bit;
344 signal nc_0_enable_to_pad : bit;
345 signal nc_10_enable_to_pad : bit;
346 signal nc_11_enable_to_pad : bit;
347 signal nc_12_enable_to_pad : bit;
348 signal nc_13_enable_to_pad : bit;
349 signal nc_14_enable_to_pad : bit;
350 signal nc_15_enable_to_pad : bit;
351 signal nc_16_enable_to_pad : bit;
352 signal nc_17_enable_to_pad : bit;
353 signal nc_18_enable_to_pad : bit;
354 signal nc_19_enable_to_pad : bit;
355 signal nc_1_enable_to_pad : bit;
356 signal nc_20_enable_to_pad : bit;
357 signal nc_21_enable_to_pad : bit;
358 signal nc_22_enable_to_pad : bit;
359 signal nc_23_enable_to_pad : bit;
360 signal nc_24_enable_to_pad : bit;
361 signal nc_25_enable_to_pad : bit;
362 signal nc_26_enable_to_pad : bit;
363 signal nc_27_enable_to_pad : bit;
364 signal nc_28_enable_to_pad : bit;
365 signal nc_29_enable_to_pad : bit;
366 signal nc_2_enable_to_pad : bit;
367 signal nc_30_enable_to_pad : bit;
368 signal nc_31_enable_to_pad : bit;
369 signal nc_32_enable_to_pad : bit;
370 signal nc_33_enable_to_pad : bit;
371 signal nc_34_enable_to_pad : bit;
372 signal nc_35_enable_to_pad : bit;
373 signal nc_36_enable_to_pad : bit;
374 signal nc_37_enable_to_pad : bit;
375 signal nc_38_enable_to_pad : bit;
376 signal nc_39_enable_to_pad : bit;
377 signal nc_3_enable_to_pad : bit;
378 signal nc_4_enable_to_pad : bit;
379 signal nc_5_enable_to_pad : bit;
380 signal nc_6_enable_to_pad : bit;
381 signal nc_7_enable_to_pad : bit;
382 signal nc_8_enable_to_pad : bit;
383 signal nc_9_enable_to_pad : bit;
384 signal sdram_a_0_enable_to_pad : bit;
385 signal sdram_a_10_enable_to_pad : bit;
386 signal sdram_a_11_enable_to_pad : bit;
387 signal sdram_a_12_enable_to_pad : bit;
388 signal sdram_a_1_enable_to_pad : bit;
389 signal sdram_a_2_enable_to_pad : bit;
390 signal sdram_a_3_enable_to_pad : bit;
391 signal sdram_a_4_enable_to_pad : bit;
392 signal sdram_a_5_enable_to_pad : bit;
393 signal sdram_a_6_enable_to_pad : bit;
394 signal sdram_a_7_enable_to_pad : bit;
395 signal sdram_a_8_enable_to_pad : bit;
396 signal sdram_a_9_enable_to_pad : bit;
397 signal sdram_ba_0_enable_to_pad : bit;
398 signal sdram_ba_1_enable_to_pad : bit;
399 signal sdram_cas_n_enable_to_pad : bit;
400 signal sdram_cas_n_to_pad : bit;
401 signal sdram_cke_enable_to_pad : bit;
402 signal sdram_cke_to_pad : bit;
403 signal sdram_clock_enable_to_pad : bit;
404 signal sdram_clock_to_pad : bit;
405 signal sdram_cs_n_enable_to_pad : bit;
406 signal sdram_cs_n_to_pad : bit;
407 signal sdram_dm_0_enable_to_pad : bit;
408 signal sdram_dm_1_enable_to_pad : bit;
409 signal sdram_ras_n_enable_to_pad : bit;
410 signal sdram_ras_n_to_pad : bit;
411 signal sdram_we_n_enable_to_pad : bit;
412 signal sdram_we_n_to_pad : bit;
413 signal spimaster_clk_enable_to_pad : bit;
414 signal spimaster_clk_to_pad : bit;
415 signal spimaster_cs_n_enable_to_pad : bit;
416 signal spimaster_cs_n_to_pad : bit;
417 signal spimaster_miso_enable_to_pad : bit;
418 signal spimaster_miso_from_pad : bit;
419 signal spimaster_mosi_enable_to_pad : bit;
420 signal spimaster_mosi_to_pad : bit;
421 signal sys_clk_enable_to_pad : bit;
422 signal sys_clk_from_pad : bit;
423 signal sys_rst_enable_to_pad : bit;
424 signal sys_rst_from_pad : bit;
425 signal uart_rx_enable_to_pad : bit;
426 signal uart_rx_from_pad : bit;
427 signal uart_tx_enable_to_pad : bit;
428 signal uart_tx_from_pad : bit;
429 signal sdram_ba_to_pad : bit_vector(1 downto 0);
430 signal sdram_dm_to_pad : bit_vector(1 downto 0);
431 signal sdram_a_to_pad : bit_vector(12 downto 0);
432 signal gpio_i_from_pad : bit_vector(15 downto 0);
433 signal gpio_o_to_pad : bit_vector(15 downto 0);
434 signal gpio_oe_to_pad : bit_vector(15 downto 0);
435 signal sdram_dq_i_from_pad : bit_vector(15 downto 0);
436 signal sdram_dq_o_to_pad : bit_vector(15 downto 0);
437 signal sdram_dq_oe_to_pad : bit_vector(15 downto 0);
438 signal nc_from_pad : bit_vector(39 downto 0);
439
440
441 begin
442
443 p_sys_rst : cmpt_gpio
444 port map ( i => sys_rst_from_pad
445 , oe => sys_rst_enable_to_pad
446 , o => chip_dummy_73
447 , pad => sys_rst
448 , iovdd => iovdd
449 , iovss => iovss
450 , vdd => vdd
451 , vss => vss
452 );
453
454 p_gpio_15 : cmpt_gpio
455 port map ( i => gpio_o_to_pad(15)
456 , oe => gpio_oe_to_pad(15)
457 , o => gpio_i_from_pad(15)
458 , pad => gpio_15
459 , iovdd => iovdd
460 , iovss => iovss
461 , vdd => vdd
462 , vss => vss
463 );
464
465 p_gpio_14 : cmpt_gpio
466 port map ( i => gpio_o_to_pad(14)
467 , oe => gpio_oe_to_pad(14)
468 , o => gpio_i_from_pad(14)
469 , pad => gpio_14
470 , iovdd => iovdd
471 , iovss => iovss
472 , vdd => vdd
473 , vss => vss
474 );
475
476 p_gpio_13 : cmpt_gpio
477 port map ( i => gpio_o_to_pad(13)
478 , oe => gpio_oe_to_pad(13)
479 , o => gpio_i_from_pad(13)
480 , pad => gpio_13
481 , iovdd => iovdd
482 , iovss => iovss
483 , vdd => vdd
484 , vss => vss
485 );
486
487 p_gpio_12 : cmpt_gpio
488 port map ( i => gpio_o_to_pad(12)
489 , oe => gpio_oe_to_pad(12)
490 , o => gpio_i_from_pad(12)
491 , pad => gpio_12
492 , iovdd => iovdd
493 , iovss => iovss
494 , vdd => vdd
495 , vss => vss
496 );
497
498 p_gpio_11 : cmpt_gpio
499 port map ( i => gpio_o_to_pad(11)
500 , oe => gpio_oe_to_pad(11)
501 , o => gpio_i_from_pad(11)
502 , pad => gpio_11
503 , iovdd => iovdd
504 , iovss => iovss
505 , vdd => vdd
506 , vss => vss
507 );
508
509 p_gpio_10 : cmpt_gpio
510 port map ( i => gpio_o_to_pad(10)
511 , oe => gpio_oe_to_pad(10)
512 , o => gpio_i_from_pad(10)
513 , pad => gpio_10
514 , iovdd => iovdd
515 , iovss => iovss
516 , vdd => vdd
517 , vss => vss
518 );
519
520 p_sdram_dm_1 : cmpt_gpio
521 port map ( i => chip_dummy_3
522 , oe => sdram_dm_1_enable_to_pad
523 , o => sdram_dm_to_pad(1)
524 , pad => sdram_dm(1)
525 , iovdd => iovdd
526 , iovss => iovss
527 , vdd => vdd
528 , vss => vss
529 );
530
531 p_sdram_dm_0 : cmpt_gpio
532 port map ( i => chip_dummy_40
533 , oe => sdram_dm_0_enable_to_pad
534 , o => sdram_dm_to_pad(0)
535 , pad => sdram_dm(0)
536 , iovdd => iovdd
537 , iovss => iovss
538 , vdd => vdd
539 , vss => vss
540 );
541
542 nc_39 : cmpt_gpio
543 port map ( i => nc_from_pad(39)
544 , oe => nc_39_enable_to_pad
545 , o => chip_dummy_78
546 , pad => nc(39)
547 , iovdd => iovdd
548 , iovss => iovss
549 , vdd => vdd
550 , vss => vss
551 );
552
553 nc_38 : cmpt_gpio
554 port map ( i => nc_from_pad(38)
555 , oe => nc_38_enable_to_pad
556 , o => chip_dummy_77
557 , pad => nc(38)
558 , iovdd => iovdd
559 , iovss => iovss
560 , vdd => vdd
561 , vss => vss
562 );
563
564 nc_37 : cmpt_gpio
565 port map ( i => nc_from_pad(37)
566 , oe => nc_37_enable_to_pad
567 , o => chip_dummy_76
568 , pad => nc(37)
569 , iovdd => iovdd
570 , iovss => iovss
571 , vdd => vdd
572 , vss => vss
573 );
574
575 nc_36 : cmpt_gpio
576 port map ( i => nc_from_pad(36)
577 , oe => nc_36_enable_to_pad
578 , o => chip_dummy_75
579 , pad => nc(36)
580 , iovdd => iovdd
581 , iovss => iovss
582 , vdd => vdd
583 , vss => vss
584 );
585
586 nc_35 : cmpt_gpio
587 port map ( i => nc_from_pad(35)
588 , oe => nc_35_enable_to_pad
589 , o => chip_dummy_74
590 , pad => nc(35)
591 , iovdd => iovdd
592 , iovss => iovss
593 , vdd => vdd
594 , vss => vss
595 );
596
597 nc_34 : cmpt_gpio
598 port map ( i => nc_from_pad(34)
599 , oe => nc_34_enable_to_pad
600 , o => chip_dummy_69
601 , pad => nc(34)
602 , iovdd => iovdd
603 , iovss => iovss
604 , vdd => vdd
605 , vss => vss
606 );
607
608 nc_33 : cmpt_gpio
609 port map ( i => nc_from_pad(33)
610 , oe => nc_33_enable_to_pad
611 , o => chip_dummy_64
612 , pad => nc(33)
613 , iovdd => iovdd
614 , iovss => iovss
615 , vdd => vdd
616 , vss => vss
617 );
618
619 nc_32 : cmpt_gpio
620 port map ( i => nc_from_pad(32)
621 , oe => nc_32_enable_to_pad
622 , o => chip_dummy_63
623 , pad => nc(32)
624 , iovdd => iovdd
625 , iovss => iovss
626 , vdd => vdd
627 , vss => vss
628 );
629
630 nc_31 : cmpt_gpio
631 port map ( i => nc_from_pad(31)
632 , oe => nc_31_enable_to_pad
633 , o => chip_dummy_62
634 , pad => nc(31)
635 , iovdd => iovdd
636 , iovss => iovss
637 , vdd => vdd
638 , vss => vss
639 );
640
641 nc_30 : cmpt_gpio
642 port map ( i => nc_from_pad(30)
643 , oe => nc_30_enable_to_pad
644 , o => chip_dummy_61
645 , pad => nc(30)
646 , iovdd => iovdd
647 , iovss => iovss
648 , vdd => vdd
649 , vss => vss
650 );
651
652 p_sdram_dq_7 : cmpt_gpio
653 port map ( i => sdram_dq_o_to_pad(7)
654 , oe => sdram_dq_oe_to_pad(7)
655 , o => sdram_dq_i_from_pad(7)
656 , pad => sdram_dq_7
657 , iovdd => iovdd
658 , iovss => iovss
659 , vdd => vdd
660 , vss => vss
661 );
662
663 p_sdram_dq_9 : cmpt_gpio
664 port map ( i => sdram_dq_o_to_pad(9)
665 , oe => sdram_dq_oe_to_pad(9)
666 , o => sdram_dq_i_from_pad(9)
667 , pad => sdram_dq_9
668 , iovdd => iovdd
669 , iovss => iovss
670 , vdd => vdd
671 , vss => vss
672 );
673
674 p_sdram_dq_8 : cmpt_gpio
675 port map ( i => sdram_dq_o_to_pad(8)
676 , oe => sdram_dq_oe_to_pad(8)
677 , o => sdram_dq_i_from_pad(8)
678 , pad => sdram_dq_8
679 , iovdd => iovdd
680 , iovss => iovss
681 , vdd => vdd
682 , vss => vss
683 );
684
685 p_sdram_dq_0 : cmpt_gpio
686 port map ( i => sdram_dq_o_to_pad(0)
687 , oe => sdram_dq_oe_to_pad(0)
688 , o => sdram_dq_i_from_pad(0)
689 , pad => sdram_dq_0
690 , iovdd => iovdd
691 , iovss => iovss
692 , vdd => vdd
693 , vss => vss
694 );
695
696 p_sdram_dq_1 : cmpt_gpio
697 port map ( i => sdram_dq_o_to_pad(1)
698 , oe => sdram_dq_oe_to_pad(1)
699 , o => sdram_dq_i_from_pad(1)
700 , pad => sdram_dq_1
701 , iovdd => iovdd
702 , iovss => iovss
703 , vdd => vdd
704 , vss => vss
705 );
706
707 p_sdram_dq_2 : cmpt_gpio
708 port map ( i => sdram_dq_o_to_pad(2)
709 , oe => sdram_dq_oe_to_pad(2)
710 , o => sdram_dq_i_from_pad(2)
711 , pad => sdram_dq_2
712 , iovdd => iovdd
713 , iovss => iovss
714 , vdd => vdd
715 , vss => vss
716 );
717
718 p_sdram_dq_3 : cmpt_gpio
719 port map ( i => sdram_dq_o_to_pad(3)
720 , oe => sdram_dq_oe_to_pad(3)
721 , o => sdram_dq_i_from_pad(3)
722 , pad => sdram_dq_3
723 , iovdd => iovdd
724 , iovss => iovss
725 , vdd => vdd
726 , vss => vss
727 );
728
729 p_sdram_dq_4 : cmpt_gpio
730 port map ( i => sdram_dq_o_to_pad(4)
731 , oe => sdram_dq_oe_to_pad(4)
732 , o => sdram_dq_i_from_pad(4)
733 , pad => sdram_dq_4
734 , iovdd => iovdd
735 , iovss => iovss
736 , vdd => vdd
737 , vss => vss
738 );
739
740 p_sdram_dq_5 : cmpt_gpio
741 port map ( i => sdram_dq_o_to_pad(5)
742 , oe => sdram_dq_oe_to_pad(5)
743 , o => sdram_dq_i_from_pad(5)
744 , pad => sdram_dq_5
745 , iovdd => iovdd
746 , iovss => iovss
747 , vdd => vdd
748 , vss => vss
749 );
750
751 p_sdram_dq_6 : cmpt_gpio
752 port map ( i => sdram_dq_o_to_pad(6)
753 , oe => sdram_dq_oe_to_pad(6)
754 , o => sdram_dq_i_from_pad(6)
755 , pad => sdram_dq_6
756 , iovdd => iovdd
757 , iovss => iovss
758 , vdd => vdd
759 , vss => vss
760 );
761
762 p_uart_rx : cmpt_gpio
763 port map ( i => uart_rx_from_pad
764 , oe => uart_rx_enable_to_pad
765 , o => chip_dummy_71
766 , pad => uart_rx
767 , iovdd => iovdd
768 , iovss => iovss
769 , vdd => vdd
770 , vss => vss
771 );
772
773 p_spimaster_mosi : cmpt_gpio
774 port map ( i => chip_dummy_67
775 , oe => spimaster_mosi_enable_to_pad
776 , o => spimaster_mosi_to_pad
777 , pad => spimaster_mosi
778 , iovdd => iovdd
779 , iovss => iovss
780 , vdd => vdd
781 , vss => vss
782 );
783
784 p_sdram_ba_1 : cmpt_gpio
785 port map ( i => chip_dummy_52
786 , oe => sdram_ba_1_enable_to_pad
787 , o => sdram_ba_to_pad(1)
788 , pad => sdram_ba(1)
789 , iovdd => iovdd
790 , iovss => iovss
791 , vdd => vdd
792 , vss => vss
793 );
794
795 p_sdram_ba_0 : cmpt_gpio
796 port map ( i => chip_dummy_51
797 , oe => sdram_ba_0_enable_to_pad
798 , o => sdram_ba_to_pad(0)
799 , pad => sdram_ba(0)
800 , iovdd => iovdd
801 , iovss => iovss
802 , vdd => vdd
803 , vss => vss
804 );
805
806 p_i2c_scl : cmpt_gpio
807 port map ( i => chip_dummy_60
808 , oe => i2c_scl_enable_to_pad
809 , o => i2c_scl_to_pad
810 , pad => i2c_scl
811 , iovdd => iovdd
812 , iovss => iovss
813 , vdd => vdd
814 , vss => vss
815 );
816
817 p_vdd_4 : cmpt_vdd
818 port map ( iovdd => iovdd
819 , iovss => iovss
820 , vdd => vdd
821 , vss => vss
822 );
823
824 p_vdd_1 : cmpt_vdd
825 port map ( iovdd => iovdd
826 , iovss => iovss
827 , vdd => vdd
828 , vss => vss
829 );
830
831 p_vdd_0 : cmpt_vdd
832 port map ( iovdd => iovdd
833 , iovss => iovss
834 , vdd => vdd
835 , vss => vss
836 );
837
838 p_vdd_2 : cmpt_vdd
839 port map ( iovdd => iovdd
840 , iovss => iovss
841 , vdd => vdd
842 , vss => vss
843 );
844
845 p_vdd_3 : cmpt_vdd
846 port map ( iovdd => iovdd
847 , iovss => iovss
848 , vdd => vdd
849 , vss => vss
850 );
851
852 p_sdram_cs_n : cmpt_gpio
853 port map ( i => chip_dummy_58
854 , oe => sdram_cs_n_enable_to_pad
855 , o => sdram_cs_n_to_pad
856 , pad => sdram_cs_n
857 , iovdd => iovdd
858 , iovss => iovss
859 , vdd => vdd
860 , vss => vss
861 );
862
863 p_iovss_0 : cmpt_iovss
864 port map ( iovdd => iovdd
865 , iovss => iovss
866 , vdd => vdd
867 , vss => vss
868 );
869
870 p_iovss_2 : cmpt_iovss
871 port map ( iovdd => iovdd
872 , iovss => iovss
873 , vdd => vdd
874 , vss => vss
875 );
876
877 p_iovss_1 : cmpt_iovss
878 port map ( iovdd => iovdd
879 , iovss => iovss
880 , vdd => vdd
881 , vss => vss
882 );
883
884 p_sys_clk : cmpt_gpio
885 port map ( i => sys_clk_from_pad
886 , oe => sys_clk_enable_to_pad
887 , o => chip_dummy_72
888 , pad => sys_clk
889 , iovdd => iovdd
890 , iovss => iovss
891 , vdd => vdd
892 , vss => vss
893 );
894
895 p_i2c_sda : cmpt_gpio
896 port map ( i => i2c_sda_o_to_pad
897 , oe => i2c_sda_oe_to_pad
898 , o => i2c_sda_i_from_pad
899 , pad => i2c_sda
900 , iovdd => iovdd
901 , iovss => iovss
902 , vdd => vdd
903 , vss => vss
904 );
905
906 p_sdram_a_10 : cmpt_gpio
907 port map ( i => chip_dummy_0
908 , oe => sdram_a_10_enable_to_pad
909 , o => sdram_a_to_pad(10)
910 , pad => sdram_a(10)
911 , iovdd => iovdd
912 , iovss => iovss
913 , vdd => vdd
914 , vss => vss
915 );
916
917 p_sdram_a_11 : cmpt_gpio
918 port map ( i => chip_dummy_1
919 , oe => sdram_a_11_enable_to_pad
920 , o => sdram_a_to_pad(11)
921 , pad => sdram_a(11)
922 , iovdd => iovdd
923 , iovss => iovss
924 , vdd => vdd
925 , vss => vss
926 );
927
928 p_sdram_a_12 : cmpt_gpio
929 port map ( i => chip_dummy_2
930 , oe => sdram_a_12_enable_to_pad
931 , o => sdram_a_to_pad(12)
932 , pad => sdram_a(12)
933 , iovdd => iovdd
934 , iovss => iovss
935 , vdd => vdd
936 , vss => vss
937 );
938
939 p_uart_tx : cmpt_gpio
940 port map ( i => uart_tx_from_pad
941 , oe => uart_tx_enable_to_pad
942 , o => chip_dummy_70
943 , pad => uart_tx
944 , iovdd => iovdd
945 , iovss => iovss
946 , vdd => vdd
947 , vss => vss
948 );
949
950 nc_0 : cmpt_gpio
951 port map ( i => nc_from_pad(0)
952 , oe => nc_0_enable_to_pad
953 , o => chip_dummy_4
954 , pad => nc(0)
955 , iovdd => iovdd
956 , iovss => iovss
957 , vdd => vdd
958 , vss => vss
959 );
960
961 p_jtag_tck : cmpt_gpio
962 port map ( i => jtag_tck_from_pad
963 , oe => jtag_tck_enable_to_pad
964 , o => chip_dummy_8
965 , pad => jtag_tck
966 , iovdd => iovdd
967 , iovss => iovss
968 , vdd => vdd
969 , vss => vss
970 );
971
972 nc_1 : cmpt_gpio
973 port map ( i => nc_from_pad(1)
974 , oe => nc_1_enable_to_pad
975 , o => chip_dummy_9
976 , pad => nc(1)
977 , iovdd => iovdd
978 , iovss => iovss
979 , vdd => vdd
980 , vss => vss
981 );
982
983 nc_2 : cmpt_gpio
984 port map ( i => nc_from_pad(2)
985 , oe => nc_2_enable_to_pad
986 , o => chip_dummy_10
987 , pad => nc(2)
988 , iovdd => iovdd
989 , iovss => iovss
990 , vdd => vdd
991 , vss => vss
992 );
993
994 nc_3 : cmpt_gpio
995 port map ( i => nc_from_pad(3)
996 , oe => nc_3_enable_to_pad
997 , o => chip_dummy_11
998 , pad => nc(3)
999 , iovdd => iovdd
1000 , iovss => iovss
1001 , vdd => vdd
1002 , vss => vss
1003 );
1004
1005 nc_4 : cmpt_gpio
1006 port map ( i => nc_from_pad(4)
1007 , oe => nc_4_enable_to_pad
1008 , o => chip_dummy_12
1009 , pad => nc(4)
1010 , iovdd => iovdd
1011 , iovss => iovss
1012 , vdd => vdd
1013 , vss => vss
1014 );
1015
1016 nc_5 : cmpt_gpio
1017 port map ( i => nc_from_pad(5)
1018 , oe => nc_5_enable_to_pad
1019 , o => chip_dummy_13
1020 , pad => nc(5)
1021 , iovdd => iovdd
1022 , iovss => iovss
1023 , vdd => vdd
1024 , vss => vss
1025 );
1026
1027 nc_6 : cmpt_gpio
1028 port map ( i => nc_from_pad(6)
1029 , oe => nc_6_enable_to_pad
1030 , o => chip_dummy_17
1031 , pad => nc(6)
1032 , iovdd => iovdd
1033 , iovss => iovss
1034 , vdd => vdd
1035 , vss => vss
1036 );
1037
1038 nc_7 : cmpt_gpio
1039 port map ( i => nc_from_pad(7)
1040 , oe => nc_7_enable_to_pad
1041 , o => chip_dummy_18
1042 , pad => nc(7)
1043 , iovdd => iovdd
1044 , iovss => iovss
1045 , vdd => vdd
1046 , vss => vss
1047 );
1048
1049 nc_8 : cmpt_gpio
1050 port map ( i => nc_from_pad(8)
1051 , oe => nc_8_enable_to_pad
1052 , o => chip_dummy_19
1053 , pad => nc(8)
1054 , iovdd => iovdd
1055 , iovss => iovss
1056 , vdd => vdd
1057 , vss => vss
1058 );
1059
1060 nc_9 : cmpt_gpio
1061 port map ( i => nc_from_pad(9)
1062 , oe => nc_9_enable_to_pad
1063 , o => chip_dummy_20
1064 , pad => nc(9)
1065 , iovdd => iovdd
1066 , iovss => iovss
1067 , vdd => vdd
1068 , vss => vss
1069 );
1070
1071 p_sdram_ras_n : cmpt_gpio
1072 port map ( i => chip_dummy_55
1073 , oe => sdram_ras_n_enable_to_pad
1074 , o => sdram_ras_n_to_pad
1075 , pad => sdram_ras_n
1076 , iovdd => iovdd
1077 , iovss => iovss
1078 , vdd => vdd
1079 , vss => vss
1080 );
1081
1082 p_jtag_tdo : cmpt_gpio
1083 port map ( i => chip_dummy_7
1084 , oe => jtag_tdo_enable_to_pad
1085 , o => jtag_tdo_to_pad
1086 , pad => jtag_tdo
1087 , iovdd => iovdd
1088 , iovss => iovss
1089 , vdd => vdd
1090 , vss => vss
1091 );
1092
1093 p_jtag_tdi : cmpt_gpio
1094 port map ( i => jtag_tdi_from_pad
1095 , oe => jtag_tdi_enable_to_pad
1096 , o => chip_dummy_6
1097 , pad => jtag_tdi
1098 , iovdd => iovdd
1099 , iovss => iovss
1100 , vdd => vdd
1101 , vss => vss
1102 );
1103
1104 p_vss_4 : cmpt_vss
1105 port map ( iovdd => iovdd
1106 , iovss => iovss
1107 , vdd => vdd
1108 , vss => vss
1109 );
1110
1111 p_vss_1 : cmpt_vss
1112 port map ( iovdd => iovdd
1113 , iovss => iovss
1114 , vdd => vdd
1115 , vss => vss
1116 );
1117
1118 p_vss_0 : cmpt_vss
1119 port map ( iovdd => iovdd
1120 , iovss => iovss
1121 , vdd => vdd
1122 , vss => vss
1123 );
1124
1125 p_vss_2 : cmpt_vss
1126 port map ( iovdd => iovdd
1127 , iovss => iovss
1128 , vdd => vdd
1129 , vss => vss
1130 );
1131
1132 p_vss_3 : cmpt_vss
1133 port map ( iovdd => iovdd
1134 , iovss => iovss
1135 , vdd => vdd
1136 , vss => vss
1137 );
1138
1139 p_spimaster_miso : cmpt_gpio
1140 port map ( i => spimaster_miso_from_pad
1141 , oe => spimaster_miso_enable_to_pad
1142 , o => chip_dummy_68
1143 , pad => spimaster_miso
1144 , iovdd => iovdd
1145 , iovss => iovss
1146 , vdd => vdd
1147 , vss => vss
1148 );
1149
1150 p_spimaster_cs_n : cmpt_gpio
1151 port map ( i => chip_dummy_66
1152 , oe => spimaster_cs_n_enable_to_pad
1153 , o => spimaster_cs_n_to_pad
1154 , pad => spimaster_cs_n
1155 , iovdd => iovdd
1156 , iovss => iovss
1157 , vdd => vdd
1158 , vss => vss
1159 );
1160
1161 p_spimaster_clk : cmpt_gpio
1162 port map ( i => chip_dummy_65
1163 , oe => spimaster_clk_enable_to_pad
1164 , o => spimaster_clk_to_pad
1165 , pad => spimaster_clk
1166 , iovdd => iovdd
1167 , iovss => iovss
1168 , vdd => vdd
1169 , vss => vss
1170 );
1171
1172 p_sdram_we_n : cmpt_gpio
1173 port map ( i => chip_dummy_57
1174 , oe => sdram_we_n_enable_to_pad
1175 , o => sdram_we_n_to_pad
1176 , pad => sdram_we_n
1177 , iovdd => iovdd
1178 , iovss => iovss
1179 , vdd => vdd
1180 , vss => vss
1181 );
1182
1183 p_sdram_a_6 : cmpt_gpio
1184 port map ( i => chip_dummy_47
1185 , oe => sdram_a_6_enable_to_pad
1186 , o => sdram_a_to_pad(6)
1187 , pad => sdram_a(6)
1188 , iovdd => iovdd
1189 , iovss => iovss
1190 , vdd => vdd
1191 , vss => vss
1192 );
1193
1194 p_sdram_a_5 : cmpt_gpio
1195 port map ( i => chip_dummy_46
1196 , oe => sdram_a_5_enable_to_pad
1197 , o => sdram_a_to_pad(5)
1198 , pad => sdram_a(5)
1199 , iovdd => iovdd
1200 , iovss => iovss
1201 , vdd => vdd
1202 , vss => vss
1203 );
1204
1205 p_sdram_a_4 : cmpt_gpio
1206 port map ( i => chip_dummy_45
1207 , oe => sdram_a_4_enable_to_pad
1208 , o => sdram_a_to_pad(4)
1209 , pad => sdram_a(4)
1210 , iovdd => iovdd
1211 , iovss => iovss
1212 , vdd => vdd
1213 , vss => vss
1214 );
1215
1216 p_sdram_a_3 : cmpt_gpio
1217 port map ( i => chip_dummy_44
1218 , oe => sdram_a_3_enable_to_pad
1219 , o => sdram_a_to_pad(3)
1220 , pad => sdram_a(3)
1221 , iovdd => iovdd
1222 , iovss => iovss
1223 , vdd => vdd
1224 , vss => vss
1225 );
1226
1227 p_sdram_a_2 : cmpt_gpio
1228 port map ( i => chip_dummy_43
1229 , oe => sdram_a_2_enable_to_pad
1230 , o => sdram_a_to_pad(2)
1231 , pad => sdram_a(2)
1232 , iovdd => iovdd
1233 , iovss => iovss
1234 , vdd => vdd
1235 , vss => vss
1236 );
1237
1238 p_sdram_a_1 : cmpt_gpio
1239 port map ( i => chip_dummy_42
1240 , oe => sdram_a_1_enable_to_pad
1241 , o => sdram_a_to_pad(1)
1242 , pad => sdram_a(1)
1243 , iovdd => iovdd
1244 , iovss => iovss
1245 , vdd => vdd
1246 , vss => vss
1247 );
1248
1249 p_sdram_a_0 : cmpt_gpio
1250 port map ( i => chip_dummy_41
1251 , oe => sdram_a_0_enable_to_pad
1252 , o => sdram_a_to_pad(0)
1253 , pad => sdram_a(0)
1254 , iovdd => iovdd
1255 , iovss => iovss
1256 , vdd => vdd
1257 , vss => vss
1258 );
1259
1260 p_sdram_a_9 : cmpt_gpio
1261 port map ( i => chip_dummy_50
1262 , oe => sdram_a_9_enable_to_pad
1263 , o => sdram_a_to_pad(9)
1264 , pad => sdram_a(9)
1265 , iovdd => iovdd
1266 , iovss => iovss
1267 , vdd => vdd
1268 , vss => vss
1269 );
1270
1271 p_sdram_a_8 : cmpt_gpio
1272 port map ( i => chip_dummy_49
1273 , oe => sdram_a_8_enable_to_pad
1274 , o => sdram_a_to_pad(8)
1275 , pad => sdram_a(8)
1276 , iovdd => iovdd
1277 , iovss => iovss
1278 , vdd => vdd
1279 , vss => vss
1280 );
1281
1282 p_sdram_a_7 : cmpt_gpio
1283 port map ( i => chip_dummy_48
1284 , oe => sdram_a_7_enable_to_pad
1285 , o => sdram_a_to_pad(7)
1286 , pad => sdram_a(7)
1287 , iovdd => iovdd
1288 , iovss => iovss
1289 , vdd => vdd
1290 , vss => vss
1291 );
1292
1293 p_jtag_tms : cmpt_gpio
1294 port map ( i => jtag_tms_from_pad
1295 , oe => jtag_tms_enable_to_pad
1296 , o => chip_dummy_5
1297 , pad => jtag_tms
1298 , iovdd => iovdd
1299 , iovss => iovss
1300 , vdd => vdd
1301 , vss => vss
1302 );
1303
1304 p_sdram_cke : cmpt_gpio
1305 port map ( i => chip_dummy_54
1306 , oe => sdram_cke_enable_to_pad
1307 , o => sdram_cke_to_pad
1308 , pad => sdram_cke
1309 , iovdd => iovdd
1310 , iovss => iovss
1311 , vdd => vdd
1312 , vss => vss
1313 );
1314
1315 corona : corona_cts_r
1316 port map ( eint_0_from_pad => eint_0_from_pad
1317 , eint_1_from_pad => eint_1_from_pad
1318 , eint_2_from_pad => eint_2_from_pad
1319 , i2c_sda_i_from_pad => i2c_sda_i_from_pad
1320 , jtag_tck_from_pad => jtag_tck_from_pad
1321 , jtag_tdi_from_pad => jtag_tdi_from_pad
1322 , jtag_tms_from_pad => jtag_tms_from_pad
1323 , spimaster_miso_from_pad => spimaster_miso_from_pad
1324 , sys_clk_from_pad => sys_clk_from_pad
1325 , sys_rst_from_pad => sys_rst_from_pad
1326 , uart_rx_from_pad => uart_rx_from_pad
1327 , uart_tx_from_pad => uart_tx_from_pad
1328 , gpio_i_from_pad => gpio_i_from_pad(15 downto 0)
1329 , sdram_dq_i_from_pad => sdram_dq_i_from_pad(15 downto 0)
1330 , nc_from_pad => nc_from_pad(39 downto 0)
1331 , eint_0_enable_to_pad => eint_0_enable_to_pad
1332 , eint_1_enable_to_pad => eint_1_enable_to_pad
1333 , eint_2_enable_to_pad => eint_2_enable_to_pad
1334 , i2c_scl_enable_to_pad => i2c_scl_enable_to_pad
1335 , i2c_scl_to_pad => i2c_scl_to_pad
1336 , i2c_sda_o_to_pad => i2c_sda_o_to_pad
1337 , i2c_sda_oe_to_pad => i2c_sda_oe_to_pad
1338 , jtag_tck_enable_to_pad => jtag_tck_enable_to_pad
1339 , jtag_tdi_enable_to_pad => jtag_tdi_enable_to_pad
1340 , jtag_tdo_enable_to_pad => jtag_tdo_enable_to_pad
1341 , jtag_tdo_to_pad => jtag_tdo_to_pad
1342 , jtag_tms_enable_to_pad => jtag_tms_enable_to_pad
1343 , nc_0_enable_to_pad => nc_0_enable_to_pad
1344 , nc_10_enable_to_pad => nc_10_enable_to_pad
1345 , nc_11_enable_to_pad => nc_11_enable_to_pad
1346 , nc_12_enable_to_pad => nc_12_enable_to_pad
1347 , nc_13_enable_to_pad => nc_13_enable_to_pad
1348 , nc_14_enable_to_pad => nc_14_enable_to_pad
1349 , nc_15_enable_to_pad => nc_15_enable_to_pad
1350 , nc_16_enable_to_pad => nc_16_enable_to_pad
1351 , nc_17_enable_to_pad => nc_17_enable_to_pad
1352 , nc_18_enable_to_pad => nc_18_enable_to_pad
1353 , nc_19_enable_to_pad => nc_19_enable_to_pad
1354 , nc_1_enable_to_pad => nc_1_enable_to_pad
1355 , nc_20_enable_to_pad => nc_20_enable_to_pad
1356 , nc_21_enable_to_pad => nc_21_enable_to_pad
1357 , nc_22_enable_to_pad => nc_22_enable_to_pad
1358 , nc_23_enable_to_pad => nc_23_enable_to_pad
1359 , nc_24_enable_to_pad => nc_24_enable_to_pad
1360 , nc_25_enable_to_pad => nc_25_enable_to_pad
1361 , nc_26_enable_to_pad => nc_26_enable_to_pad
1362 , nc_27_enable_to_pad => nc_27_enable_to_pad
1363 , nc_28_enable_to_pad => nc_28_enable_to_pad
1364 , nc_29_enable_to_pad => nc_29_enable_to_pad
1365 , nc_2_enable_to_pad => nc_2_enable_to_pad
1366 , nc_30_enable_to_pad => nc_30_enable_to_pad
1367 , nc_31_enable_to_pad => nc_31_enable_to_pad
1368 , nc_32_enable_to_pad => nc_32_enable_to_pad
1369 , nc_33_enable_to_pad => nc_33_enable_to_pad
1370 , nc_34_enable_to_pad => nc_34_enable_to_pad
1371 , nc_35_enable_to_pad => nc_35_enable_to_pad
1372 , nc_36_enable_to_pad => nc_36_enable_to_pad
1373 , nc_37_enable_to_pad => nc_37_enable_to_pad
1374 , nc_38_enable_to_pad => nc_38_enable_to_pad
1375 , nc_39_enable_to_pad => nc_39_enable_to_pad
1376 , nc_3_enable_to_pad => nc_3_enable_to_pad
1377 , nc_4_enable_to_pad => nc_4_enable_to_pad
1378 , nc_5_enable_to_pad => nc_5_enable_to_pad
1379 , nc_6_enable_to_pad => nc_6_enable_to_pad
1380 , nc_7_enable_to_pad => nc_7_enable_to_pad
1381 , nc_8_enable_to_pad => nc_8_enable_to_pad
1382 , nc_9_enable_to_pad => nc_9_enable_to_pad
1383 , sdram_a_0_enable_to_pad => sdram_a_0_enable_to_pad
1384 , sdram_a_10_enable_to_pad => sdram_a_10_enable_to_pad
1385 , sdram_a_11_enable_to_pad => sdram_a_11_enable_to_pad
1386 , sdram_a_12_enable_to_pad => sdram_a_12_enable_to_pad
1387 , sdram_a_1_enable_to_pad => sdram_a_1_enable_to_pad
1388 , sdram_a_2_enable_to_pad => sdram_a_2_enable_to_pad
1389 , sdram_a_3_enable_to_pad => sdram_a_3_enable_to_pad
1390 , sdram_a_4_enable_to_pad => sdram_a_4_enable_to_pad
1391 , sdram_a_5_enable_to_pad => sdram_a_5_enable_to_pad
1392 , sdram_a_6_enable_to_pad => sdram_a_6_enable_to_pad
1393 , sdram_a_7_enable_to_pad => sdram_a_7_enable_to_pad
1394 , sdram_a_8_enable_to_pad => sdram_a_8_enable_to_pad
1395 , sdram_a_9_enable_to_pad => sdram_a_9_enable_to_pad
1396 , sdram_ba_0_enable_to_pad => sdram_ba_0_enable_to_pad
1397 , sdram_ba_1_enable_to_pad => sdram_ba_1_enable_to_pad
1398 , sdram_cas_n_enable_to_pad => sdram_cas_n_enable_to_pad
1399 , sdram_cas_n_to_pad => sdram_cas_n_to_pad
1400 , sdram_cke_enable_to_pad => sdram_cke_enable_to_pad
1401 , sdram_cke_to_pad => sdram_cke_to_pad
1402 , sdram_clock_enable_to_pad => sdram_clock_enable_to_pad
1403 , sdram_clock_to_pad => sdram_clock_to_pad
1404 , sdram_cs_n_enable_to_pad => sdram_cs_n_enable_to_pad
1405 , sdram_cs_n_to_pad => sdram_cs_n_to_pad
1406 , sdram_dm_0_enable_to_pad => sdram_dm_0_enable_to_pad
1407 , sdram_dm_1_enable_to_pad => sdram_dm_1_enable_to_pad
1408 , sdram_ras_n_enable_to_pad => sdram_ras_n_enable_to_pad
1409 , sdram_ras_n_to_pad => sdram_ras_n_to_pad
1410 , sdram_we_n_enable_to_pad => sdram_we_n_enable_to_pad
1411 , sdram_we_n_to_pad => sdram_we_n_to_pad
1412 , spimaster_clk_enable_to_pad => spimaster_clk_enable_to_pad
1413 , spimaster_clk_to_pad => spimaster_clk_to_pad
1414 , spimaster_cs_n_enable_to_pad => spimaster_cs_n_enable_to_pad
1415 , spimaster_cs_n_to_pad => spimaster_cs_n_to_pad
1416 , spimaster_miso_enable_to_pad => spimaster_miso_enable_to_pad
1417 , spimaster_mosi_enable_to_pad => spimaster_mosi_enable_to_pad
1418 , spimaster_mosi_to_pad => spimaster_mosi_to_pad
1419 , sys_clk_enable_to_pad => sys_clk_enable_to_pad
1420 , sys_rst_enable_to_pad => sys_rst_enable_to_pad
1421 , uart_rx_enable_to_pad => uart_rx_enable_to_pad
1422 , uart_tx_enable_to_pad => uart_tx_enable_to_pad
1423 , sdram_ba_to_pad => sdram_ba_to_pad(1 downto 0)
1424 , sdram_dm_to_pad => sdram_dm_to_pad(1 downto 0)
1425 , sdram_a_to_pad => sdram_a_to_pad(12 downto 0)
1426 , gpio_o_to_pad => gpio_o_to_pad(15 downto 0)
1427 , gpio_oe_to_pad => gpio_oe_to_pad(15 downto 0)
1428 , sdram_dq_o_to_pad => sdram_dq_o_to_pad(15 downto 0)
1429 , sdram_dq_oe_to_pad => sdram_dq_oe_to_pad(15 downto 0)
1430 , vdd => vdd
1431 , vss => vss
1432 );
1433
1434 p_gpio_7 : cmpt_gpio
1435 port map ( i => gpio_o_to_pad(7)
1436 , oe => gpio_oe_to_pad(7)
1437 , o => gpio_i_from_pad(7)
1438 , pad => gpio_7
1439 , iovdd => iovdd
1440 , iovss => iovss
1441 , vdd => vdd
1442 , vss => vss
1443 );
1444
1445 p_gpio_6 : cmpt_gpio
1446 port map ( i => gpio_o_to_pad(6)
1447 , oe => gpio_oe_to_pad(6)
1448 , o => gpio_i_from_pad(6)
1449 , pad => gpio_6
1450 , iovdd => iovdd
1451 , iovss => iovss
1452 , vdd => vdd
1453 , vss => vss
1454 );
1455
1456 p_gpio_5 : cmpt_gpio
1457 port map ( i => gpio_o_to_pad(5)
1458 , oe => gpio_oe_to_pad(5)
1459 , o => gpio_i_from_pad(5)
1460 , pad => gpio_5
1461 , iovdd => iovdd
1462 , iovss => iovss
1463 , vdd => vdd
1464 , vss => vss
1465 );
1466
1467 p_gpio_4 : cmpt_gpio
1468 port map ( i => gpio_o_to_pad(4)
1469 , oe => gpio_oe_to_pad(4)
1470 , o => gpio_i_from_pad(4)
1471 , pad => gpio_4
1472 , iovdd => iovdd
1473 , iovss => iovss
1474 , vdd => vdd
1475 , vss => vss
1476 );
1477
1478 p_gpio_3 : cmpt_gpio
1479 port map ( i => gpio_o_to_pad(3)
1480 , oe => gpio_oe_to_pad(3)
1481 , o => gpio_i_from_pad(3)
1482 , pad => gpio_3
1483 , iovdd => iovdd
1484 , iovss => iovss
1485 , vdd => vdd
1486 , vss => vss
1487 );
1488
1489 p_gpio_2 : cmpt_gpio
1490 port map ( i => gpio_o_to_pad(2)
1491 , oe => gpio_oe_to_pad(2)
1492 , o => gpio_i_from_pad(2)
1493 , pad => gpio_2
1494 , iovdd => iovdd
1495 , iovss => iovss
1496 , vdd => vdd
1497 , vss => vss
1498 );
1499
1500 p_gpio_1 : cmpt_gpio
1501 port map ( i => gpio_o_to_pad(1)
1502 , oe => gpio_oe_to_pad(1)
1503 , o => gpio_i_from_pad(1)
1504 , pad => gpio_1
1505 , iovdd => iovdd
1506 , iovss => iovss
1507 , vdd => vdd
1508 , vss => vss
1509 );
1510
1511 p_gpio_0 : cmpt_gpio
1512 port map ( i => gpio_o_to_pad(0)
1513 , oe => gpio_oe_to_pad(0)
1514 , o => gpio_i_from_pad(0)
1515 , pad => gpio_0
1516 , iovdd => iovdd
1517 , iovss => iovss
1518 , vdd => vdd
1519 , vss => vss
1520 );
1521
1522 p_sdram_clock : cmpt_gpio
1523 port map ( i => chip_dummy_53
1524 , oe => sdram_clock_enable_to_pad
1525 , o => sdram_clock_to_pad
1526 , pad => sdram_clock
1527 , iovdd => iovdd
1528 , iovss => iovss
1529 , vdd => vdd
1530 , vss => vss
1531 );
1532
1533 p_gpio_9 : cmpt_gpio
1534 port map ( i => gpio_o_to_pad(9)
1535 , oe => gpio_oe_to_pad(9)
1536 , o => gpio_i_from_pad(9)
1537 , pad => gpio_9
1538 , iovdd => iovdd
1539 , iovss => iovss
1540 , vdd => vdd
1541 , vss => vss
1542 );
1543
1544 p_gpio_8 : cmpt_gpio
1545 port map ( i => gpio_o_to_pad(8)
1546 , oe => gpio_oe_to_pad(8)
1547 , o => gpio_i_from_pad(8)
1548 , pad => gpio_8
1549 , iovdd => iovdd
1550 , iovss => iovss
1551 , vdd => vdd
1552 , vss => vss
1553 );
1554
1555 p_sdram_dq_15 : cmpt_gpio
1556 port map ( i => sdram_dq_o_to_pad(15)
1557 , oe => sdram_dq_oe_to_pad(15)
1558 , o => sdram_dq_i_from_pad(15)
1559 , pad => sdram_dq_15
1560 , iovdd => iovdd
1561 , iovss => iovss
1562 , vdd => vdd
1563 , vss => vss
1564 );
1565
1566 p_sdram_dq_14 : cmpt_gpio
1567 port map ( i => sdram_dq_o_to_pad(14)
1568 , oe => sdram_dq_oe_to_pad(14)
1569 , o => sdram_dq_i_from_pad(14)
1570 , pad => sdram_dq_14
1571 , iovdd => iovdd
1572 , iovss => iovss
1573 , vdd => vdd
1574 , vss => vss
1575 );
1576
1577 p_sdram_dq_13 : cmpt_gpio
1578 port map ( i => sdram_dq_o_to_pad(13)
1579 , oe => sdram_dq_oe_to_pad(13)
1580 , o => sdram_dq_i_from_pad(13)
1581 , pad => sdram_dq_13
1582 , iovdd => iovdd
1583 , iovss => iovss
1584 , vdd => vdd
1585 , vss => vss
1586 );
1587
1588 p_sdram_dq_12 : cmpt_gpio
1589 port map ( i => sdram_dq_o_to_pad(12)
1590 , oe => sdram_dq_oe_to_pad(12)
1591 , o => sdram_dq_i_from_pad(12)
1592 , pad => sdram_dq_12
1593 , iovdd => iovdd
1594 , iovss => iovss
1595 , vdd => vdd
1596 , vss => vss
1597 );
1598
1599 p_sdram_dq_11 : cmpt_gpio
1600 port map ( i => sdram_dq_o_to_pad(11)
1601 , oe => sdram_dq_oe_to_pad(11)
1602 , o => sdram_dq_i_from_pad(11)
1603 , pad => sdram_dq_11
1604 , iovdd => iovdd
1605 , iovss => iovss
1606 , vdd => vdd
1607 , vss => vss
1608 );
1609
1610 p_sdram_dq_10 : cmpt_gpio
1611 port map ( i => sdram_dq_o_to_pad(10)
1612 , oe => sdram_dq_oe_to_pad(10)
1613 , o => sdram_dq_i_from_pad(10)
1614 , pad => sdram_dq_10
1615 , iovdd => iovdd
1616 , iovss => iovss
1617 , vdd => vdd
1618 , vss => vss
1619 );
1620
1621 p_eint_0 : cmpt_gpio
1622 port map ( i => eint_0_from_pad
1623 , oe => eint_0_enable_to_pad
1624 , o => chip_dummy_14
1625 , pad => eint_0
1626 , iovdd => iovdd
1627 , iovss => iovss
1628 , vdd => vdd
1629 , vss => vss
1630 );
1631
1632 p_eint_1 : cmpt_gpio
1633 port map ( i => eint_1_from_pad
1634 , oe => eint_1_enable_to_pad
1635 , o => chip_dummy_15
1636 , pad => eint_1
1637 , iovdd => iovdd
1638 , iovss => iovss
1639 , vdd => vdd
1640 , vss => vss
1641 );
1642
1643 p_eint_2 : cmpt_gpio
1644 port map ( i => eint_2_from_pad
1645 , oe => eint_2_enable_to_pad
1646 , o => chip_dummy_16
1647 , pad => eint_2
1648 , iovdd => iovdd
1649 , iovss => iovss
1650 , vdd => vdd
1651 , vss => vss
1652 );
1653
1654 nc_10 : cmpt_gpio
1655 port map ( i => nc_from_pad(10)
1656 , oe => nc_10_enable_to_pad
1657 , o => chip_dummy_21
1658 , pad => nc(10)
1659 , iovdd => iovdd
1660 , iovss => iovss
1661 , vdd => vdd
1662 , vss => vss
1663 );
1664
1665 nc_11 : cmpt_gpio
1666 port map ( i => nc_from_pad(11)
1667 , oe => nc_11_enable_to_pad
1668 , o => chip_dummy_22
1669 , pad => nc(11)
1670 , iovdd => iovdd
1671 , iovss => iovss
1672 , vdd => vdd
1673 , vss => vss
1674 );
1675
1676 nc_12 : cmpt_gpio
1677 port map ( i => nc_from_pad(12)
1678 , oe => nc_12_enable_to_pad
1679 , o => chip_dummy_23
1680 , pad => nc(12)
1681 , iovdd => iovdd
1682 , iovss => iovss
1683 , vdd => vdd
1684 , vss => vss
1685 );
1686
1687 nc_13 : cmpt_gpio
1688 port map ( i => nc_from_pad(13)
1689 , oe => nc_13_enable_to_pad
1690 , o => chip_dummy_24
1691 , pad => nc(13)
1692 , iovdd => iovdd
1693 , iovss => iovss
1694 , vdd => vdd
1695 , vss => vss
1696 );
1697
1698 nc_14 : cmpt_gpio
1699 port map ( i => nc_from_pad(14)
1700 , oe => nc_14_enable_to_pad
1701 , o => chip_dummy_25
1702 , pad => nc(14)
1703 , iovdd => iovdd
1704 , iovss => iovss
1705 , vdd => vdd
1706 , vss => vss
1707 );
1708
1709 nc_15 : cmpt_gpio
1710 port map ( i => nc_from_pad(15)
1711 , oe => nc_15_enable_to_pad
1712 , o => chip_dummy_26
1713 , pad => nc(15)
1714 , iovdd => iovdd
1715 , iovss => iovss
1716 , vdd => vdd
1717 , vss => vss
1718 );
1719
1720 nc_16 : cmpt_gpio
1721 port map ( i => nc_from_pad(16)
1722 , oe => nc_16_enable_to_pad
1723 , o => chip_dummy_27
1724 , pad => nc(16)
1725 , iovdd => iovdd
1726 , iovss => iovss
1727 , vdd => vdd
1728 , vss => vss
1729 );
1730
1731 nc_17 : cmpt_gpio
1732 port map ( i => nc_from_pad(17)
1733 , oe => nc_17_enable_to_pad
1734 , o => chip_dummy_28
1735 , pad => nc(17)
1736 , iovdd => iovdd
1737 , iovss => iovss
1738 , vdd => vdd
1739 , vss => vss
1740 );
1741
1742 nc_18 : cmpt_gpio
1743 port map ( i => nc_from_pad(18)
1744 , oe => nc_18_enable_to_pad
1745 , o => chip_dummy_29
1746 , pad => nc(18)
1747 , iovdd => iovdd
1748 , iovss => iovss
1749 , vdd => vdd
1750 , vss => vss
1751 );
1752
1753 nc_19 : cmpt_gpio
1754 port map ( i => nc_from_pad(19)
1755 , oe => nc_19_enable_to_pad
1756 , o => chip_dummy_30
1757 , pad => nc(19)
1758 , iovdd => iovdd
1759 , iovss => iovss
1760 , vdd => vdd
1761 , vss => vss
1762 );
1763
1764 p_sdram_cas_n : cmpt_gpio
1765 port map ( i => chip_dummy_56
1766 , oe => sdram_cas_n_enable_to_pad
1767 , o => sdram_cas_n_to_pad
1768 , pad => sdram_cas_n
1769 , iovdd => iovdd
1770 , iovss => iovss
1771 , vdd => vdd
1772 , vss => vss
1773 );
1774
1775 p_iovdd_0 : cmpt_iovdd
1776 port map ( iovdd => iovdd
1777 , iovss => iovss
1778 , vdd => vdd
1779 , vss => vss
1780 );
1781
1782 p_iovdd_2 : cmpt_iovdd
1783 port map ( iovdd => iovdd
1784 , iovss => iovss
1785 , vdd => vdd
1786 , vss => vss
1787 );
1788
1789 p_iovdd_1 : cmpt_iovdd
1790 port map ( iovdd => iovdd
1791 , iovss => iovss
1792 , vdd => vdd
1793 , vss => vss
1794 );
1795
1796 nc_29 : cmpt_gpio
1797 port map ( i => nc_from_pad(29)
1798 , oe => nc_29_enable_to_pad
1799 , o => chip_dummy_59
1800 , pad => nc(29)
1801 , iovdd => iovdd
1802 , iovss => iovss
1803 , vdd => vdd
1804 , vss => vss
1805 );
1806
1807 nc_20 : cmpt_gpio
1808 port map ( i => nc_from_pad(20)
1809 , oe => nc_20_enable_to_pad
1810 , o => chip_dummy_31
1811 , pad => nc(20)
1812 , iovdd => iovdd
1813 , iovss => iovss
1814 , vdd => vdd
1815 , vss => vss
1816 );
1817
1818 nc_21 : cmpt_gpio
1819 port map ( i => nc_from_pad(21)
1820 , oe => nc_21_enable_to_pad
1821 , o => chip_dummy_32
1822 , pad => nc(21)
1823 , iovdd => iovdd
1824 , iovss => iovss
1825 , vdd => vdd
1826 , vss => vss
1827 );
1828
1829 nc_22 : cmpt_gpio
1830 port map ( i => nc_from_pad(22)
1831 , oe => nc_22_enable_to_pad
1832 , o => chip_dummy_33
1833 , pad => nc(22)
1834 , iovdd => iovdd
1835 , iovss => iovss
1836 , vdd => vdd
1837 , vss => vss
1838 );
1839
1840 nc_23 : cmpt_gpio
1841 port map ( i => nc_from_pad(23)
1842 , oe => nc_23_enable_to_pad
1843 , o => chip_dummy_34
1844 , pad => nc(23)
1845 , iovdd => iovdd
1846 , iovss => iovss
1847 , vdd => vdd
1848 , vss => vss
1849 );
1850
1851 nc_24 : cmpt_gpio
1852 port map ( i => nc_from_pad(24)
1853 , oe => nc_24_enable_to_pad
1854 , o => chip_dummy_35
1855 , pad => nc(24)
1856 , iovdd => iovdd
1857 , iovss => iovss
1858 , vdd => vdd
1859 , vss => vss
1860 );
1861
1862 nc_25 : cmpt_gpio
1863 port map ( i => nc_from_pad(25)
1864 , oe => nc_25_enable_to_pad
1865 , o => chip_dummy_36
1866 , pad => nc(25)
1867 , iovdd => iovdd
1868 , iovss => iovss
1869 , vdd => vdd
1870 , vss => vss
1871 );
1872
1873 nc_26 : cmpt_gpio
1874 port map ( i => nc_from_pad(26)
1875 , oe => nc_26_enable_to_pad
1876 , o => chip_dummy_37
1877 , pad => nc(26)
1878 , iovdd => iovdd
1879 , iovss => iovss
1880 , vdd => vdd
1881 , vss => vss
1882 );
1883
1884 nc_27 : cmpt_gpio
1885 port map ( i => nc_from_pad(27)
1886 , oe => nc_27_enable_to_pad
1887 , o => chip_dummy_38
1888 , pad => nc(27)
1889 , iovdd => iovdd
1890 , iovss => iovss
1891 , vdd => vdd
1892 , vss => vss
1893 );
1894
1895 nc_28 : cmpt_gpio
1896 port map ( i => nc_from_pad(28)
1897 , oe => nc_28_enable_to_pad
1898 , o => chip_dummy_39
1899 , pad => nc(28)
1900 , iovdd => iovdd
1901 , iovss => iovss
1902 , vdd => vdd
1903 , vss => vss
1904 );
1905
1906 end structural;
1907