3 """makes corrections to vst source from coriolis2 P&R
11 USE IEEE.std_logic_1164.ALL;
12 USE IEEE.numeric_std.ALL;
15 # run through all files
16 for fname
in os
.listdir("vst_src"):
17 if not fname
.endswith(".vst"):
20 is_chip
= fname
.startswith("chip")
22 fname
= "vst_src/"+fname
23 with
open(fname
) as f
:
25 # replace vss / vdd : linkage bit with vss/vdd in bit
26 txt
= txt
.replace("linkage bit", "in bit")
27 # and double-underscores
28 txt
= txt
.replace("__", "_")
29 # special-case for chip.vst and chip_r.vst
31 # add VHDL IEEE Library header
32 txt
= vhdl_header
+ txt
34 txt
= txt
.replace("pad : inout mux_bit bus",
35 "pad : inout std_logic")
37 txt
= txt
.replace("sys_rst : gpio",
40 # corona instance needs renaming too
41 txt
= txt
.replace("corona : corona", "instance_corona : corona")
43 # temporary hack to rename niolib to avoid name-clashes
44 for cell
in ['gpio', 'vss', 'vdd', 'iovss', 'iovdd']:
45 txt
= txt
.replace(": %s" % cell
, ": cmpt_%s" % cell
)
46 txt
= txt
.replace("component %s" % cell
, "component cmpt_%s" % cell
)
47 # identify the chip ports and replace "in bit" with "inout std_logic"
51 for line
in txt
.splitlines():
56 if line
.startswith("entity chip"):
60 for port
in ['vss', 'vdd', 'iovss', 'iovdd']:
61 if ' %s ' % port
in line
and 'in bit' in line
:
64 # covers in bit_vector and out bit_vector as well
65 line
= line
.replace("in bit", "inout std_logic")
66 line
= line
.replace("out bit", "inout std_logic")
67 done_chip
= line
.startswith("end chip")
73 with
open(fname
, "w") as f
: