use git submodule soclayout for source files, rather than

[soc-cocotb-sim.git] / ls180 / experiment9_recon / Makefile

diff --git a/ls180/experiment9_recon/Makefile b/ls180/experiment9_recon/Makefile
index 68efc45c2cc8c5781a98c4638a344626cd04bbc9..9942b9c27afbfb703343038e3e87a810aa3aa84f 100644 (file)
--- a/ls180/experiment9_recon/Makefile
+++ b/ls180/experiment9_recon/Makefile
@@ -9,8 +9,7 @@ TOPLEVEL_LANG := verilog
 VERILOG_SOURCES := \
   ../spblock_512w64b8w.v \
   ../pll.v \
-  full_core_4_4ksram_libresoc_recon.v \
-  full_core_4_4ksram_litex_ls180_recon.v \
+  ls180.v
 # END VERILOG_SOURCES
 
 MODULE := test