use git submodule soclayout for source files, rather than

[soc-cocotb-sim.git] / ls180 / post_pnr / Makefile

diff --git a/ls180/post_pnr/Makefile b/ls180/post_pnr/Makefile
index c0a63c8bb687ce941f3f85bb266cc2de7ef1efbd..feeea4fdd7aa71b835a0866259c63858d81b134b 100644 (file)
--- a/ls180/post_pnr/Makefile
+++ b/ls180/post_pnr/Makefile
@@ -1,4 +1,4 @@
-.PHONY: all corona prepare cocotb gitupdate
+.PHONY: all chip prepare cocotb gitupdate
 
 all: prepare cocotb
 
@@ -16,8 +16,12 @@ cocotb:
        (cd cocotb && ./run_ghdl.sh)
 
 # builds just for fun (double-check) ghdl works
-corona:
+chip:
        ./vhd2obj.py
-       (cd obj && ghdl -e -g --std=08 corona)
-       (cd obj && ghdl -r -g --std=08 corona)
+       (cd obj && ghdl -e -g --std=08 chip)
+       (cd obj && ghdl -r -g --std=08 chip)
 
+# imports all ghdl "stuff" and outputs verilog
+chip_v: chip
+       (cd obj && yosys -m ghdl -p 'ghdl --std=08 chip' \
+        -p 'proc' -p 'write_verilog chip.v')