sorting out cts (post p&r)

[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb / Makefile

diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile
index 360364aacf7460dce6707ecf0cd5752c17ff9770..9cd849af9df3b0fe00f4a922cbbbc114a36c0126 100644 (file)
--- a/ls180/post_pnr/cocotb/Makefile
+++ b/ls180/post_pnr/cocotb/Makefile
@@ -9,13 +9,16 @@ endif
 export PYTHONPATH
 
 VSTDIR=$(TOPDIR)/vst_src
+CHIPDIR=$(TOPDIR)/chip_corona
 NSXLIBDIR=$(TOPDIR)/nsxlib
 NIOLIBDIR=$(TOPDIR)/niolib
 VHDL_SOURCES = \
+  $(CHIPDIR)/chip_r.vhd \
+  $(CHIPDIR)/corona_cts_r.vhd \
   $(wildcard $(VSTDIR)/*.vst) \
   $(wildcard $(NSXLIBDIR)/*.vhd) \
   $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=ls180
+TOPLEVEL=chip_r
 TOPLEVEL_LANG=vhdl
 MODULE=test
 SIM=ghdl