sort out build of chip/corona using experiments10_verilog

[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb / Makefile

diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile
index a53c81bd318903f679b4d2a3788956ae84bb6e73..bf1bfcf51720db6d6449aa766707fe522ce5f570 100644 (file)
--- a/ls180/post_pnr/cocotb/Makefile
+++ b/ls180/post_pnr/cocotb/Makefile
@@ -9,7 +9,7 @@ endif
 export PYTHONPATH
 
 VSTDIR=$(TOPDIR)/vst_src
-CHIPDIR=$(TOPDIR)/chip_corona
+#CHIPDIR=$(TOPDIR)/chip_corona
 NSXLIBDIR=$(TOPDIR)/nsxlib
 NIOLIBDIR=$(TOPDIR)/niolib
 #  $(CHIPDIR)/chip_r.vhd 
@@ -18,7 +18,7 @@ VHDL_SOURCES = \
   $(wildcard $(VSTDIR)/*.vst) \
   $(wildcard $(NSXLIBDIR)/*.vhd) \
   $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=chip_r
+TOPLEVEL=chip
 TOPLEVEL_LANG=vhdl
 MODULE ?= test
 SIM=ghdl