fix iovdd/iovss in-to-std_logic conversion

[soc-cocotb-sim.git] / ls180 / post_pnr / vst_correct.py

diff --git a/ls180/post_pnr/vst_correct.py b/ls180/post_pnr/vst_correct.py
index 0f454660241d8c40f376e191f7244af3b64c687c..e11ccc0a015f602191ec71a76634c70ec0d26063 100755 (executable)
--- a/ls180/post_pnr/vst_correct.py
+++ b/ls180/post_pnr/vst_correct.py
@@ -56,18 +56,18 @@ for fname in os.listdir("vst_src"):
                 if line.startswith("entity chip"):
                     found_chip = True
             else:
-                # covers in bit_vector and out bit_vector as well
-                line = line.replace("in bit", "inout std_logic")
-                line = line.replace("out bit", "inout std_logic")
+                is_power = False
+                for port in ['vss', 'vdd', 'iovss', 'iovdd']:
+                    if ' %s ' % port in line and 'in bit' in line:
+                        is_power = True
+                if not is_power:
+                    # covers in bit_vector and out bit_vector as well
+                    line = line.replace("in bit", "inout std_logic")
+                    line = line.replace("out bit", "inout std_logic")
                 done_chip = line.startswith("end chip")
             res.append(line)
         # re-join lines
         txt = '\n'.join(res)
-        # easier to just post-process-correct the iovdd std_logic
-        for port in ['vss', 'vdd', 'iovss', 'iovdd']:
-            txt = txt.replace("%-9s: inout std_logic" % port,
-                              "%-9s: in bit" % port)
-
         
     # write the file
     with open(fname, "w") as f: