get pre-coriolis2 verilator (wishbone) functional

[soc-cocotb-sim.git] / ls180 / pre_pnr / run_verilator_ls180.sh

diff --git a/ls180/pre_pnr/run_verilator_ls180.sh b/ls180/pre_pnr/run_verilator_ls180.sh
new file mode 100755 (executable)
index 0000000..e618edf
--- /dev/null
+++ b/ls180/pre_pnr/run_verilator_ls180.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+# create dummy memory files
+yes 0 | head -128 > mem_1.init 
+yes 0 | head -32 > mem_1.init 
+touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
+
+# Only run test in reset state as running CPU takes too much time to simulate
+make \
+  SIM=verilator \
+  TOPLEVEL=ls180 \
+  COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \
+  COCOTB_HDL_TIMEUNIT=100ps \
+  TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset,idcode_run" \
+  VERILATOR_TRACE="1" \
+  NOTUSEDCOMPILE_ARGS="--unroll-count 256 \
+        --output-split 5000 \
+        --output-split-cfuncs 500 \
+        --output-split-ctrace 500 \
+        -Wno-fatal \
+        -Wno-BLKANDNBLK \
+        -Wno-WIDTH" \
+  MODULE="test" \
+  SIM_BUILD=sim_build_iverilator_ls180
+
+
+