remove async, use yield

[soc-cocotb-sim.git] / ls180 / pre_pnr / testwb.py

diff --git a/ls180/pre_pnr/testwb.py b/ls180/pre_pnr/testwb.py
index 6e19eaa08382c9b1432d98d041fa1730af215399..098558e62e2a8f714f49d1b59799a1c2ecf37cc9 100644 (file)
--- a/ls180/pre_pnr/testwb.py
+++ b/ls180/pre_pnr/testwb.py
@@ -134,7 +134,7 @@ def get_jtag_boundary():
     return pins
 
 
-async def setup_sim(dut, *, info, clk_period, run):
+def setup_sim(dut, *, info, clk_period, run):
     """Initialize CPU and setup clock"""
 
     wrap = DUTWrapper(dut)
@@ -146,14 +146,10 @@ async def setup_sim(dut, *, info, clk_period, run):
     clk_steps = get_sim_steps(clk_period, "ns")
     cocotb.fork(Clock(wrap.clk, clk_steps).start())
 
-
     if run:
-        for _ in range(2):
-            await RisingEdge(wrap.clk)
+        yield Timer(int(10.5*clk_steps))
         wrap.rst <= 0
-        for _ in range(1):
-            await RisingEdge(wrap.clk)
-        #await Timer(int(3*clk_steps))
+        yield Timer(int(3*clk_steps))
 
     return wrap
 
@@ -161,30 +157,31 @@ async def setup_sim(dut, *, info, clk_period, run):
 def setup_jtag(wrap, *, tck_period):
     # TODO: Make this a generator
     if False:
-        await Timer(0)
+        yield Timer(0)
+    clk_steps = get_sim_steps(tck_period, "ns")
     return JTAG_Master(wrap.tck, wrap.tms, wrap.tdi, wrap.tdo,
-                       clk_period=tck_period,
+                       clk_period=clk_steps,
                        ir_width=4)
 
-async def execute_svf(wrap, *, jtag, svf_filename):
-    await jtag.reset()
+def execute_svf(wrap, *, jtag, svf_filename):
+    yield jtag.reset()
 
     jtag_svf = SVF_Executor(jtag)
     with open(svf_filename, "r") as f:
         svf_deck = f.read()
-    await jtag_svf.run(svf_deck, p=wrap.info)
+    yield jtag_svf.run(svf_deck, p=wrap.info)
 
 #
 # IDCODE using JTAG_master
 #
 
-async def idcode(wrap, *, jtag):
-    await jtag.idcode()
+def idcode(wrap, *, jtag):
+    yield jtag.idcode()
     result1 = jtag.result
     wrap.info("IDCODE1: {}".format(result1))
     assert(result1 == BinaryValue("00000000000000000001100011111111"))
 
-    await jtag.idcode()
+    yield jtag.idcode()
     result2 = jtag.result
     wrap.info("IDCODE2: {}".format(result2))
 
@@ -192,31 +189,31 @@ async def idcode(wrap, *, jtag):
 
 
 @cocotb.test()
-async def idcode_reset(dut):
+def idcode_reset(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE test; cpu in reset..."
-    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
                                 run=False)
-    jtag = await setup_jtag(wrap, tck_period = tck_period)
+    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
 
-    await idcode(wrap, jtag=jtag)
+    yield from idcode(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-async def idcode_run(dut):
+def idcode_run(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE test; cpu running..."
-    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
                          run=True)
-    jtag = await setup_jtag(wrap, tck_period = tck_period)
+    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
 
-    await idcode(wrap, jtag=jtag)
+    yield from idcode(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
@@ -225,31 +222,31 @@ async def idcode_run(dut):
 #
 
 @cocotb.test()
-async def idcodesvf_reset(dut):
+def idcodesvf_reset(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE through SVF test; cpu in reset..."
-    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
                                 run=False)
-    jtag = await setup_jtag(wrap, tck_period = tck_period)
+    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
 
-    await execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
+    yield from execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-async def idcodesvf_run(dut):
+def idcodesvf_run(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE through SVF test; cpu running..."
-    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
                                 run=True)
-    jtag = await setup_jtag(wrap, tck_period = tck_period)
+    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
 
-    await execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
+    yield from execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
 
     wrap.info("IDCODE test completed")
 
@@ -257,19 +254,19 @@ async def idcodesvf_run(dut):
 # Boundary scan
 #
 
-async def boundary_scan(wrap, *, jtag):
+def boundary_scan(wrap, *, jtag):
     pins = get_jtag_boundary()
 
-    await jtag.reset()
+    yield jtag.reset()
 
     wrap.info("")
     wrap.info("Before scan")
     log_pins(wrap, pins)
 
-    await jtag.load_ir([0, 0, 0, 0])
+    yield jtag.load_ir([0, 0, 0, 0])
     pinsdata = tuple(pin.data(i=i%2, o=((i%3)%2), oe=((i%5)%2))
                      for i, pin in enumerate(pins))
-    await jtag.shift_data(chain(*pinsdata))
+    yield jtag.shift_data(chain(*pinsdata))
 
     wrap.info("")
     wrap.info("After scan")
@@ -277,7 +274,7 @@ async def boundary_scan(wrap, *, jtag):
     for i, pin in enumerate(pins):
         pin.check(wrap=wrap, i=i%2, o=((i%3)%2), oe=((i%5)%2))
 
-    await jtag.reset()
+    yield jtag.reset()
 
     wrap.info("")
     wrap.info("After reset")
@@ -285,42 +282,42 @@ async def boundary_scan(wrap, *, jtag):
 
 
 @cocotb.test()
-async def boundary_scan_reset(dut):
+def boundary_scan_reset(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running boundary scan test; cpu in reset..."
-    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
                                 run=False)
-    jtag = await setup_jtag(wrap, tck_period = tck_period)
+    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
 
-    await boundary_scan(wrap, jtag=jtag)
+    yield from boundary_scan(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-async def boundary_scan_run(dut):
+def boundary_scan_run(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running boundary scan test; cpu running..."
-    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
                                 run=True)
-    jtag = await setup_jtag(wrap, tck_period = tck_period)
+    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
 
-    await boundary_scan(wrap, jtag=jtag)
+    yield from boundary_scan(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-async def wishbone_basic(dut):
+def wishbone_basic(dut):
     """
     Test of an added Wishbone interface
     """
     clk_period = 100 # 10MHz
-    tck_period = 30000 # 0.3MHz
+    tck_period = 300 # 0.3MHz
 
     data_in = BinaryValue()
     # these have to match with soc.debug.jtag.JTAG ircodes
@@ -329,117 +326,117 @@ async def wishbone_basic(dut):
     cmd_MEMREADWRITE = BinaryValue("0111")  # 7
 
     info = "Running Wishbone basic test"
-    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
                                 run=True)
-    master = await setup_jtag(wrap, tck_period = tck_period)
+    master = yield from setup_jtag(wrap, tck_period = tck_period)
 
 
     #clk_steps = get_sim_steps(clk_period, "ns")
-    #await Timer(int(4.5*clk_steps))
+    #yield Timer(int(4.5*clk_steps))
     #wrap.rst <= 0
 
-    #await master.reset()
+    #yield master.reset()
 
-    #await Timer(int(10.5*clk_steps))
+    #yield Timer(int(10.5*clk_steps))
 
     #wrap.rst <= 0
 
     # Load the memory address
-    await master.load_ir(cmd_MEMADDRESS)
+    yield master.load_ir(cmd_MEMADDRESS)
     dut._log.info("Loading address")
 
     data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
     # Do write
-    await master.load_ir(cmd_MEMREADWRITE)
+    yield master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Writing memory")
 
     data_in.binstr = "01010101" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
     data_in.binstr = "10101010" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
     # Load the memory address
-    await master.load_ir(cmd_MEMADDRESS)
+    yield master.load_ir(cmd_MEMADDRESS)
     dut._log.info("Loading address")
 
     data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "000000000000000000000000000000"
 
     # Do read and write
-    await master.load_ir(cmd_MEMREADWRITE)
+    yield master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Reading and writing memory")
 
     data_in.binstr = "10101010" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "01010101" * 4
 
     data_in.binstr = "01010101" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "10101010" * 4
 
     # Load the memory address
-    await master.load_ir(cmd_MEMADDRESS)
+    yield master.load_ir(cmd_MEMADDRESS)
     dut._log.info("Loading address")
 
     data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "00000000000000000000000000010"
 
     # Do read
-    await master.load_ir(cmd_MEMREAD)
+    yield master.load_ir(cmd_MEMREAD)
     dut._log.info("Reading memory")
     data_in.binstr = "00000000" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "10101010" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "01010101" * 4
 
     # Load the memory address
-    await master.load_ir(cmd_MEMADDRESS) # MEMADDR
+    yield master.load_ir(cmd_MEMADDRESS) # MEMADDR
     dut._log.info("Loading address")
 
     data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "00000000000000000000000000010"
 
     # Do read
-    await master.load_ir(cmd_MEMREAD) # MEMREAD
+    yield master.load_ir(cmd_MEMREAD) # MEMREAD
     dut._log.info("Reading memory")
     data_in.binstr = "00000000" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "10101010" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    await master.shift_data(data_in)
+    yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "01010101" * 4