use git submodule soclayout for source files, rather than master
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 18:30:08 +0000 (19:30 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 18:30:08 +0000 (19:30 +0100)
commit (yet another) copy of an auto-generated file
TODO: replace all other duplicated copies of additional files,
there are now half a dozen copies of pll.v for example

.gitmodules
ls180/experiment9_recon/Makefile
ls180/experiment9_recon/run_iverilog_ls180.sh
soclayout [new submodule]

index 663524b55ae5123d249ed5780f7317d3469ef236..ba7ad5b1caee0ff168f9d28572e4317e804197af 100644 (file)
@@ -1,3 +1,6 @@
 [submodule "alliance-check-toolkit"]
        path = alliance-check-toolkit
        url = https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit.git
+[submodule "soclayout"]
+       path = soclayout
+       url = git://libre-soc.org/soclayout.git
index 68efc45c2cc8c5781a98c4638a344626cd04bbc9..9942b9c27afbfb703343038e3e87a810aa3aa84f 100644 (file)
@@ -9,8 +9,7 @@ TOPLEVEL_LANG := verilog
 VERILOG_SOURCES := \
   ../spblock_512w64b8w.v \
   ../pll.v \
-  full_core_4_4ksram_libresoc_recon.v \
-  full_core_4_4ksram_litex_ls180_recon.v \
+  ls180.v
 # END VERILOG_SOURCES
 
 MODULE := test
index eae098658c633a07ef7fc4a433c17267c49953df..9dba6e64ec0d02913989c66873dc1541161cb0a3 100755 (executable)
@@ -1,5 +1,11 @@
 #!/bin/sh
 
+SRCDIR=../../soclayout/experiments9/non_generated/
+cp $SRCDIR/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
+cp $SRCDIR/full_core_4_4ksram_libresoc_recon.v libresoc.v
+cp $SRCDIR/pll.v .
+cp $SRCDIR/ls180.v .
+
 touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
 # Only run test in reset state as running CPU takes too much time to simulate
 make \
diff --git a/soclayout b/soclayout
new file mode 160000 (submodule)
index 0000000..4f3fce3
--- /dev/null
+++ b/soclayout
@@ -0,0 +1 @@
+Subproject commit 4f3fce32074946c452fe9089cec271a6d5843e59