upload 32-bit wishbone data not 64-bit test data

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 718faf562c7bdf0bfcf8678201e1d79579bbd6a2..a96846c670d6a512f136e6d1c036c0dee2788d04 100644 (file)
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -172,12 +172,12 @@ def wishbone_basic(dut):
     yield master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Writing memory")
 
-    data_in.binstr = "01010101" * 8
+    data_in.binstr = "01010101" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
-    data_in.binstr = "10101010" * 8
+    data_in.binstr = "10101010" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))