From: Luke Kenneth Casson Leighton Date: Thu, 1 Apr 2021 21:29:35 +0000 (+0100) Subject: move post-pnr to new subdirectory X-Git-Url: https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=commitdiff_plain;h=f51fd1c0dd1be2f51f712b883a57e8d266dedbe0 move post-pnr to new subdirectory --- diff --git a/ls180/.gitignore b/ls180/.gitignore deleted file mode 100644 index 88a919e..0000000 --- a/ls180/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -niolib/ -nsxlib/ -obj/ -vst_src/ -__pycache__/ -.*.sw? diff --git a/ls180/Makefile b/ls180/Makefile deleted file mode 100644 index c0a63c8..0000000 --- a/ls180/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -.PHONY: all corona prepare cocotb gitupdate - -all: prepare cocotb - -# submodule update -gitupdate: - git submodule update --init --remote - -# gets the nsxlib and niolib files, and munges the contents of vst_src -prepare: - ./vbe2vst.py - ./vst_correct.py - -# runs cocotb test -cocotb: - (cd cocotb && ./run_ghdl.sh) - -# builds just for fun (double-check) ghdl works -corona: - ./vhd2obj.py - (cd obj && ghdl -e -g --std=08 corona) - (cd obj && ghdl -r -g --std=08 corona) - diff --git a/ls180/README.txt b/ls180/README.txt deleted file mode 100644 index c928c5a..0000000 --- a/ls180/README.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Dependencies - -* make gitupdate -* https://git.libre-soc.org/?p=dev-env-setup.git;a=summary - - run coriolis2_chroot (to set up coriolis2) - - run install-hdl-apt-reqs -* install ghdl (working: GHDL 1.0-dev (v0.37.0-819-g9828b513) [Dunoon edition]) - this is very likely to have to be done from source -* install cocotb (can be done from source https://github.com/cocotb/cocotb) - -# Build - -* make one experiment with a JTAG tap (experiments10 or experiments9) -* copy *.vst into vst_src except cts files, chip.vst and chip_r.vst -* make cocotb diff --git a/ls180/cocotb/.gitignore b/ls180/cocotb/.gitignore deleted file mode 100644 index 9b22a82..0000000 --- a/ls180/cocotb/.gitignore +++ /dev/null @@ -1 +0,0 @@ -test.ghw diff --git a/ls180/cocotb/Makefile b/ls180/cocotb/Makefile deleted file mode 100644 index 1255036..0000000 --- a/ls180/cocotb/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -CURDIR=$(realpath .) -TOPDIR=$(realpath ..) - -ifeq ($(PYTHONPATH),) - PYTHONPATH := $(TOPDIR) -else - PYTHONPATH := $(TOPDIR):$(PYTHONPATH) -endif -export PYTHONPATH - -VSTDIR=$(TOPDIR)/vst_src -NSXLIBDIR=$(TOPDIR)/nsxlib -NIOLIBDIR=$(TOPDIR)/niolib -VHDL_SOURCES = \ - $(wildcard $(VSTDIR)/*.vst) \ - $(wildcard $(NSXLIBDIR)/*.vhd) \ - $(wildcard $(NIOLIBDIR)/*.vhd) -TOPLEVEL=corona -TOPLEVEL_LANG=vhdl -MODULE=test -SIM=ghdl -GPI_IMPL=vhpi -GHDL_ARGS=--std=08 -SIM_ARGS=--wave=test.ghw - -COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles) - -include $(COCOTBMAKEFILESDIR)/Makefile.sim diff --git a/ls180/cocotb/clean.sh b/ls180/cocotb/clean.sh deleted file mode 100755 index 04882ff..0000000 --- a/ls180/cocotb/clean.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh -rm -fr results_*.xml sim_build_* - diff --git a/ls180/cocotb/idcode.svf b/ls180/cocotb/idcode.svf deleted file mode 100644 index 994e9c8..0000000 --- a/ls180/cocotb/idcode.svf +++ /dev/null @@ -1,4 +0,0 @@ -!Loading device with 'idcode' instruction. -SIR 4 TDI (1); -SDR 32 TDI (00000000) TDO (000018FF) ; - diff --git a/ls180/cocotb/run_ghdl.sh b/ls180/cocotb/run_ghdl.sh deleted file mode 100755 index 6c5e05b..0000000 --- a/ls180/cocotb/run_ghdl.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -# Only run test in reset state as running CPU takes too much time to simulate -make \ - SIM=ghdl \ - COCOTB_RESULTS_FILE=results_iverilog.xml \ - COCOTB_HDL_TIMEUNIT=100ps \ - TESTCASE="idcode_reset,idcodesvf_reset" \ - SIM_BUILD=sim_build_iverilog - - diff --git a/ls180/cocotb/test.py b/ls180/cocotb/test.py deleted file mode 100644 index 68057e3..0000000 --- a/ls180/cocotb/test.py +++ /dev/null @@ -1,118 +0,0 @@ -import cocotb -from cocotb.clock import Clock -from cocotb.triggers import Timer -from cocotb.utils import get_sim_steps -from cocotb.binary import BinaryValue - -from c4m.cocotb.jtag.c4m_jtag import JTAG_Master -from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor - -# -# Helper functions -# - -def setup_sim(dut, *, clk_period, run): - """Initialize CPU and setup clock""" - - clk_steps = get_sim_steps(clk_period, "ns") - cocotb.fork(Clock(dut.clk_from_pad, clk_steps).start()) - - dut.rst_from_pad <= 1 - dut.clk_from_pad <= 0 - if run: - yield Timer(int(10.5*clk_steps)) - dut.rst_from_pad <= 0 - yield Timer(int(5*clk_steps)) - -def setup_jtag(dut, *, tck_period): - # Make this a generator - if False: - yield Timer(0) - return JTAG_Master(dut.tck_from_pad, dut.tms_from_pad, - dut.tdi_from_pad, dut.tdo_to_pad, - clk_period=tck_period, - ir_width=4) - -def execute_svf(dut, *, jtag, svf_filename): - jtag_svf = SVF_Executor(jtag) - with open(svf_filename, "r") as f: - svf_deck = f.read() - yield jtag_svf.run(svf_deck, p=dut._log.info) - -# -# IDCODE using JTAG_master -# - -def idcode(dut, *, jtag): - #jtag.IDCODE = [0, 0, 0, 1] - yield jtag.idcode() - result1 = jtag.result - dut._log.info("IDCODE1: {}".format(result1)) - assert(result1 == BinaryValue("00000000000000000001100011111111")) - - yield jtag.idcode() - result2 = jtag.result - dut._log.info("IDCODE2: {}".format(result2)) - - assert(result1 == result2) - -@cocotb.test() -def idcode_reset(dut): - dut._log.info("Running IDCODE test; cpu in reset...") - - clk_period = 100 # 10MHz - tck_period = 300 # 3MHz - - yield from setup_sim(dut, clk_period=clk_period, run=False) - jtag = yield from setup_jtag(dut, tck_period = tck_period) - - yield from idcode(dut, jtag=jtag) - - dut._log.info("IDCODE test completed") - -@cocotb.test() -def idcode_run(dut): - dut._log.info("Running IDCODE test; cpu running...") - - clk_period = 100 # 10MHz - tck_period = 300 # 3MHz - - yield from setup_sim(dut, clk_period=clk_period, run=True) - jtag = yield from setup_jtag(dut, tck_period = tck_period) - - yield from idcode(dut, jtag=jtag) - - dut._log.info("IDCODE test completed") - -# -# Read IDCODE from SVF file -# - -@cocotb.test() -def idcodesvf_reset(dut): - dut._log.info("Running IDCODE through SVF test; cpu in reset...") - - clk_period = 100 # 10MHz - tck_period = 300 # 3MHz - - yield from setup_sim(dut, clk_period=clk_period, run=False) - jtag = yield from setup_jtag(dut, tck_period = tck_period) - - yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf") - - dut._log.info("IDCODE test completed") - -@cocotb.test() -def idcode_run(dut): - dut._log.info("Running IDCODE through test; cpu running...") - - clk_period = 100 # 10MHz - tck_period = 300 # 3MHz - - yield from setup_sim(dut, clk_period=clk_period, run=True) - jtag = yield from setup_jtag(dut, tck_period = tck_period) - - yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf") - - dut._log.info("IDCODE test completed") - diff --git a/ls180/post_pnr/.gitignore b/ls180/post_pnr/.gitignore new file mode 100644 index 0000000..88a919e --- /dev/null +++ b/ls180/post_pnr/.gitignore @@ -0,0 +1,6 @@ +niolib/ +nsxlib/ +obj/ +vst_src/ +__pycache__/ +.*.sw? diff --git a/ls180/post_pnr/Makefile b/ls180/post_pnr/Makefile new file mode 100644 index 0000000..c0a63c8 --- /dev/null +++ b/ls180/post_pnr/Makefile @@ -0,0 +1,23 @@ +.PHONY: all corona prepare cocotb gitupdate + +all: prepare cocotb + +# submodule update +gitupdate: + git submodule update --init --remote + +# gets the nsxlib and niolib files, and munges the contents of vst_src +prepare: + ./vbe2vst.py + ./vst_correct.py + +# runs cocotb test +cocotb: + (cd cocotb && ./run_ghdl.sh) + +# builds just for fun (double-check) ghdl works +corona: + ./vhd2obj.py + (cd obj && ghdl -e -g --std=08 corona) + (cd obj && ghdl -r -g --std=08 corona) + diff --git a/ls180/post_pnr/README.txt b/ls180/post_pnr/README.txt new file mode 100644 index 0000000..c928c5a --- /dev/null +++ b/ls180/post_pnr/README.txt @@ -0,0 +1,15 @@ +# Dependencies + +* make gitupdate +* https://git.libre-soc.org/?p=dev-env-setup.git;a=summary + - run coriolis2_chroot (to set up coriolis2) + - run install-hdl-apt-reqs +* install ghdl (working: GHDL 1.0-dev (v0.37.0-819-g9828b513) [Dunoon edition]) + this is very likely to have to be done from source +* install cocotb (can be done from source https://github.com/cocotb/cocotb) + +# Build + +* make one experiment with a JTAG tap (experiments10 or experiments9) +* copy *.vst into vst_src except cts files, chip.vst and chip_r.vst +* make cocotb diff --git a/ls180/post_pnr/cocotb/.gitignore b/ls180/post_pnr/cocotb/.gitignore new file mode 100644 index 0000000..9b22a82 --- /dev/null +++ b/ls180/post_pnr/cocotb/.gitignore @@ -0,0 +1 @@ +test.ghw diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile new file mode 100644 index 0000000..1255036 --- /dev/null +++ b/ls180/post_pnr/cocotb/Makefile @@ -0,0 +1,28 @@ +CURDIR=$(realpath .) +TOPDIR=$(realpath ..) + +ifeq ($(PYTHONPATH),) + PYTHONPATH := $(TOPDIR) +else + PYTHONPATH := $(TOPDIR):$(PYTHONPATH) +endif +export PYTHONPATH + +VSTDIR=$(TOPDIR)/vst_src +NSXLIBDIR=$(TOPDIR)/nsxlib +NIOLIBDIR=$(TOPDIR)/niolib +VHDL_SOURCES = \ + $(wildcard $(VSTDIR)/*.vst) \ + $(wildcard $(NSXLIBDIR)/*.vhd) \ + $(wildcard $(NIOLIBDIR)/*.vhd) +TOPLEVEL=corona +TOPLEVEL_LANG=vhdl +MODULE=test +SIM=ghdl +GPI_IMPL=vhpi +GHDL_ARGS=--std=08 +SIM_ARGS=--wave=test.ghw + +COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles) + +include $(COCOTBMAKEFILESDIR)/Makefile.sim diff --git a/ls180/post_pnr/cocotb/clean.sh b/ls180/post_pnr/cocotb/clean.sh new file mode 100755 index 0000000..04882ff --- /dev/null +++ b/ls180/post_pnr/cocotb/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -fr results_*.xml sim_build_* + diff --git a/ls180/post_pnr/cocotb/idcode.svf b/ls180/post_pnr/cocotb/idcode.svf new file mode 100644 index 0000000..994e9c8 --- /dev/null +++ b/ls180/post_pnr/cocotb/idcode.svf @@ -0,0 +1,4 @@ +!Loading device with 'idcode' instruction. +SIR 4 TDI (1); +SDR 32 TDI (00000000) TDO (000018FF) ; + diff --git a/ls180/post_pnr/cocotb/run_ghdl.sh b/ls180/post_pnr/cocotb/run_ghdl.sh new file mode 100755 index 0000000..6c5e05b --- /dev/null +++ b/ls180/post_pnr/cocotb/run_ghdl.sh @@ -0,0 +1,11 @@ +#!/bin/sh + +# Only run test in reset state as running CPU takes too much time to simulate +make \ + SIM=ghdl \ + COCOTB_RESULTS_FILE=results_iverilog.xml \ + COCOTB_HDL_TIMEUNIT=100ps \ + TESTCASE="idcode_reset,idcodesvf_reset" \ + SIM_BUILD=sim_build_iverilog + + diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py new file mode 100644 index 0000000..68057e3 --- /dev/null +++ b/ls180/post_pnr/cocotb/test.py @@ -0,0 +1,118 @@ +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import Timer +from cocotb.utils import get_sim_steps +from cocotb.binary import BinaryValue + +from c4m.cocotb.jtag.c4m_jtag import JTAG_Master +from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor + +# +# Helper functions +# + +def setup_sim(dut, *, clk_period, run): + """Initialize CPU and setup clock""" + + clk_steps = get_sim_steps(clk_period, "ns") + cocotb.fork(Clock(dut.clk_from_pad, clk_steps).start()) + + dut.rst_from_pad <= 1 + dut.clk_from_pad <= 0 + if run: + yield Timer(int(10.5*clk_steps)) + dut.rst_from_pad <= 0 + yield Timer(int(5*clk_steps)) + +def setup_jtag(dut, *, tck_period): + # Make this a generator + if False: + yield Timer(0) + return JTAG_Master(dut.tck_from_pad, dut.tms_from_pad, + dut.tdi_from_pad, dut.tdo_to_pad, + clk_period=tck_period, + ir_width=4) + +def execute_svf(dut, *, jtag, svf_filename): + jtag_svf = SVF_Executor(jtag) + with open(svf_filename, "r") as f: + svf_deck = f.read() + yield jtag_svf.run(svf_deck, p=dut._log.info) + +# +# IDCODE using JTAG_master +# + +def idcode(dut, *, jtag): + #jtag.IDCODE = [0, 0, 0, 1] + yield jtag.idcode() + result1 = jtag.result + dut._log.info("IDCODE1: {}".format(result1)) + assert(result1 == BinaryValue("00000000000000000001100011111111")) + + yield jtag.idcode() + result2 = jtag.result + dut._log.info("IDCODE2: {}".format(result2)) + + assert(result1 == result2) + +@cocotb.test() +def idcode_reset(dut): + dut._log.info("Running IDCODE test; cpu in reset...") + + clk_period = 100 # 10MHz + tck_period = 300 # 3MHz + + yield from setup_sim(dut, clk_period=clk_period, run=False) + jtag = yield from setup_jtag(dut, tck_period = tck_period) + + yield from idcode(dut, jtag=jtag) + + dut._log.info("IDCODE test completed") + +@cocotb.test() +def idcode_run(dut): + dut._log.info("Running IDCODE test; cpu running...") + + clk_period = 100 # 10MHz + tck_period = 300 # 3MHz + + yield from setup_sim(dut, clk_period=clk_period, run=True) + jtag = yield from setup_jtag(dut, tck_period = tck_period) + + yield from idcode(dut, jtag=jtag) + + dut._log.info("IDCODE test completed") + +# +# Read IDCODE from SVF file +# + +@cocotb.test() +def idcodesvf_reset(dut): + dut._log.info("Running IDCODE through SVF test; cpu in reset...") + + clk_period = 100 # 10MHz + tck_period = 300 # 3MHz + + yield from setup_sim(dut, clk_period=clk_period, run=False) + jtag = yield from setup_jtag(dut, tck_period = tck_period) + + yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf") + + dut._log.info("IDCODE test completed") + +@cocotb.test() +def idcode_run(dut): + dut._log.info("Running IDCODE through test; cpu running...") + + clk_period = 100 # 10MHz + tck_period = 300 # 3MHz + + yield from setup_sim(dut, clk_period=clk_period, run=True) + jtag = yield from setup_jtag(dut, tck_period = tck_period) + + yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf") + + dut._log.info("IDCODE test completed") + diff --git a/ls180/post_pnr/vbe2vst.py b/ls180/post_pnr/vbe2vst.py new file mode 100755 index 0000000..7377ec9 --- /dev/null +++ b/ls180/post_pnr/vbe2vst.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +"""converts NIOLIB and NSXLIB from VBE into VHDL +""" + +import os +import sys + +# use the chroot to set up +# https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD +# reason for using the chroot: it's standardised across the ls180 project + +VASY_CMD = "schroot -c coriolis -d /tmp -- ~/alliance/install/bin/vasy" +ALLIANCEBASE = "../../alliance-check-toolkit/cells" +ALLIANCE_LIBS = ['nsxlib', 'niolib'] + +for libname in ALLIANCE_LIBS: + + NSXLIB = "%s/%s" % (ALLIANCEBASE, libname) + + os.system("mkdir -p %s" % libname) + + for fname in os.listdir(NSXLIB): + if not fname.endswith(".vbe"): + continue + print (fname) + prefix = fname[:-4] # strip ".vbe" + os.system("cp %s/%s /tmp" % (NSXLIB, fname)) + os.system("rm -f /tmp/%s.vhd" % (prefix)) + os.system("%s -s -I vbe %s %s" % (VASY_CMD, fname, prefix)) + os.system("cp /tmp/%s.vhd %s" % (prefix, libname)) diff --git a/ls180/post_pnr/vhd2obj.py b/ls180/post_pnr/vhd2obj.py new file mode 100755 index 0000000..596519e --- /dev/null +++ b/ls180/post_pnr/vhd2obj.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 + +"""builds nsxlib and other VHD files into object files using ghdl +""" + +import os +import sys + +SRC = [('nsxlib', 'vhd'), + ('niolib', 'vhd'), + ('vst_src', 'vst')] + +# make and change to obj dir +os.system("mkdir -p obj") +cwd = os.getcwd() +os.chdir("obj") + +for srcdir, suffix in SRC: + # run ghdl -a on every vhd / vst file + for fname in os.listdir("../%s" % srcdir): + if not fname.endswith(".%s" % suffix): + continue + print (fname) + prefix = fname[:-4] # strip ".vhd" + os.system("ghdl -a -g --std=08 ../%s/%s" % (srcdir, fname)) + +# back to original dir +os.chdir(cwd) diff --git a/ls180/post_pnr/vst_correct.py b/ls180/post_pnr/vst_correct.py new file mode 100755 index 0000000..68bd2a0 --- /dev/null +++ b/ls180/post_pnr/vst_correct.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 + +"""makes corrections to vst source from coriolis2 P&R +""" + +import os +import sys + +# run through all files +for fname in os.listdir("vst_src"): + if not fname.endswith(".vst"): + continue + print (fname) + # read the file + fname = "vst_src/"+fname + with open(fname) as f: + txt = f.read() + # replace vss / vdd : linkage bit with vss/vdd in bit + txt = txt.replace("linkage bit", "in bit") + # and double-underscores + txt = txt.replace("__", "_") + # write the file + with open(fname, "w") as f: + f.write(txt) diff --git a/ls180/vbe2vst.py b/ls180/vbe2vst.py deleted file mode 100755 index 075538c..0000000 --- a/ls180/vbe2vst.py +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env python3 -"""converts NIOLIB and NSXLIB from VBE into VHDL -""" - -import os -import sys - -# use the chroot to set up -# https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD -# reason for using the chroot: it's standardised across the ls180 project - -VASY_CMD = "schroot -c coriolis -d /tmp -- ~/alliance/install/bin/vasy" -ALLIANCEBASE = "../alliance-check-toolkit/cells" -ALLIANCE_LIBS = ['nsxlib', 'niolib'] - -for libname in ALLIANCE_LIBS: - - NSXLIB = "%s/%s" % (ALLIANCEBASE, libname) - - os.system("mkdir -p %s" % libname) - - for fname in os.listdir(NSXLIB): - if not fname.endswith(".vbe"): - continue - print (fname) - prefix = fname[:-4] # strip ".vbe" - os.system("cp %s/%s /tmp" % (NSXLIB, fname)) - os.system("rm -f /tmp/%s.vhd" % (prefix)) - os.system("%s -s -I vbe %s %s" % (VASY_CMD, fname, prefix)) - os.system("cp /tmp/%s.vhd %s" % (prefix, libname)) diff --git a/ls180/vhd2obj.py b/ls180/vhd2obj.py deleted file mode 100755 index 596519e..0000000 --- a/ls180/vhd2obj.py +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env python3 - -"""builds nsxlib and other VHD files into object files using ghdl -""" - -import os -import sys - -SRC = [('nsxlib', 'vhd'), - ('niolib', 'vhd'), - ('vst_src', 'vst')] - -# make and change to obj dir -os.system("mkdir -p obj") -cwd = os.getcwd() -os.chdir("obj") - -for srcdir, suffix in SRC: - # run ghdl -a on every vhd / vst file - for fname in os.listdir("../%s" % srcdir): - if not fname.endswith(".%s" % suffix): - continue - print (fname) - prefix = fname[:-4] # strip ".vhd" - os.system("ghdl -a -g --std=08 ../%s/%s" % (srcdir, fname)) - -# back to original dir -os.chdir(cwd) diff --git a/ls180/vst_correct.py b/ls180/vst_correct.py deleted file mode 100755 index 68bd2a0..0000000 --- a/ls180/vst_correct.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 - -"""makes corrections to vst source from coriolis2 P&R -""" - -import os -import sys - -# run through all files -for fname in os.listdir("vst_src"): - if not fname.endswith(".vst"): - continue - print (fname) - # read the file - fname = "vst_src/"+fname - with open(fname) as f: - txt = f.read() - # replace vss / vdd : linkage bit with vss/vdd in bit - txt = txt.replace("linkage bit", "in bit") - # and double-underscores - txt = txt.replace("__", "_") - # write the file - with open(fname, "w") as f: - f.write(txt)