use git submodule soclayout for source files, rather than
[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb /
2021-06-05 Luke Kenneth Casso... sort out build of chip/corona using experiments10_verilog
2021-04-16 Luke Kenneth Casso... upload 32-bit wishbone data not 64-bit test data
2021-04-16 Luke Kenneth Casso... corrections to wishbone test
2021-04-16 Luke Kenneth Casso... corrections to wishbone test
2021-04-14 Luke Kenneth Casso... add test boundary scan hard-coded test
2021-04-14 Luke Kenneth Casso... try chip_r adder test (works)
2021-04-13 Luke Kenneth Casso... get jtag tests running on basic adder
2021-04-13 Luke Kenneth Casso... more post-processing of vst files
2021-04-11 Luke Kenneth Casso... sorting out cts (post p&r)
2021-04-10 Luke Kenneth Casso... use vcd for wave output not ghw
2021-04-10 Luke Kenneth Casso... sigh, no wrap - use direct
2021-04-10 Luke Kenneth Casso... add ghdl wishbone basic test
2021-04-01 Luke Kenneth Casso... move post-pnr to new subdirectory