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[soc-cocotb-sim.git] / ls180 / post_pnr /
2021-06-05 Luke Kenneth Casso... sort out build of chip/corona using experiments10_verilog tree | commitdiff
2021-04-17 Luke Kenneth Casso... add verilator post-pnr cocotb sim tree | commitdiff
2021-04-17 Luke Kenneth Casso... add chip conversion from ghdl to verilog tree | commitdiff
2021-04-17 Luke Kenneth Casso... fix iovdd/iovss in-to-std_logic conversion tree | commitdiff
2021-04-16 Luke Kenneth Casso... upload 32-bit wishbone data not 64-bit test data tree | commitdiff
2021-04-16 Luke Kenneth Casso... corrections to wishbone test tree | commitdiff
2021-04-16 Luke Kenneth Casso... corrections to wishbone test tree | commitdiff
2021-04-14 Luke Kenneth Casso... add test boundary scan hard-coded test tree | commitdiff
2021-04-14 Luke Kenneth Casso... try chip_r adder test (works) tree | commitdiff
2021-04-13 Luke Kenneth Casso... get jtag tests running on basic adder tree | commitdiff
2021-04-13 Luke Kenneth Casso... more post-processing of vst files tree | commitdiff
2021-04-12 Luke Kenneth Casso... more vst corrections, for chip definition tree | commitdiff
2021-04-11 Luke Kenneth Casso... sorting out cts (post p&r) tree | commitdiff
2021-04-10 Luke Kenneth Casso... adding edited versions of chip/corona tree | commitdiff
2021-04-10 Luke Kenneth Casso... use vcd for wave output not ghw tree | commitdiff
2021-04-10 Luke Kenneth Casso... sigh, no wrap - use direct tree | commitdiff
2021-04-10 Luke Kenneth Casso... add ghdl wishbone basic test tree | commitdiff
2021-04-03 Staf VerhaegenUpdate gitignore. tree | commitdiff
2021-04-01 Luke Kenneth Casso... move post-pnr to new subdirectory tree | commitdiff