soc-cocotb-sim.git
5 months agouse git submodule soclayout for source files, rather than master
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 18:30:08 +0000 (19:30 +0100)]
use git submodule soclayout for source files, rather than
commit (yet another) copy of an auto-generated file
TODO: replace all other duplicated copies of additional files,
there are now half a dozen copies of pll.v for example

5 months agodisallow adding verilog files
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 18:07:40 +0000 (19:07 +0100)]
disallow adding verilog files

5 months agosort out build of chip/corona using experiments10_verilog
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 18:05:30 +0000 (19:05 +0100)]
sort out build of chip/corona using experiments10_verilog

5 months agoUse cocotb test on ls180/experiments9 with reconnected clock.
Staf Verhaegen [Fri, 4 Jun 2021 09:28:47 +0000 (11:28 +0200)]
Use cocotb test on ls180/experiments9 with reconnected clock.

7 months agoadd verilator post-pnr cocotb sim
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 12:22:06 +0000 (13:22 +0100)]
add verilator post-pnr cocotb sim

7 months agoadd chip conversion from ghdl to verilog
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 10:52:48 +0000 (11:52 +0100)]
add chip conversion from ghdl to verilog

7 months agofix iovdd/iovss in-to-std_logic conversion
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 10:52:38 +0000 (11:52 +0100)]
fix iovdd/iovss in-to-std_logic conversion

7 months agoget pre-coriolis2 verilator (wishbone) functional
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 22:43:36 +0000 (23:43 +0100)]
get pre-coriolis2 verilator (wishbone) functional

7 months agoupload 32-bit wishbone data not 64-bit test data
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 20:08:14 +0000 (21:08 +0100)]
upload 32-bit wishbone data not 64-bit test data

7 months agocorrections to wishbone test
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:43:28 +0000 (01:43 +0100)]
corrections to wishbone test

7 months agocorrections to wishbone test
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:41:42 +0000 (01:41 +0100)]
corrections to wishbone test

7 months agoadd test boundary scan hard-coded test
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 11:36:39 +0000 (12:36 +0100)]
add test boundary scan hard-coded test

7 months agotry chip_r adder test (works)
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 10:37:22 +0000 (11:37 +0100)]
try chip_r adder test (works)

7 months agoremove async, use yield
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 10:36:32 +0000 (11:36 +0100)]
remove async, use yield

7 months agoget jtag tests running on basic adder
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 19:18:43 +0000 (20:18 +0100)]
get jtag tests running on basic adder

7 months agoconvert wb test to async
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:39:15 +0000 (17:39 +0100)]
convert wb test to async

7 months agoresolving pin names (to litex ls180)
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:38:55 +0000 (17:38 +0100)]
resolving pin names (to litex ls180)

7 months agomore post-processing of vst files
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:38:10 +0000 (17:38 +0100)]
more post-processing of vst files

7 months agomore vst corrections, for chip definition
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 15:14:15 +0000 (16:14 +0100)]
more vst corrections, for chip definition

7 months agosorting out cts (post p&r)
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 16:06:33 +0000 (17:06 +0100)]
sorting out cts (post p&r)

7 months agoadding edited versions of chip/corona
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 19:50:36 +0000 (20:50 +0100)]
adding edited versions of chip/corona

7 months agouse vcd for wave output not ghw
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 15:39:09 +0000 (16:39 +0100)]
use vcd for wave output not ghw

7 months agosigh, no wrap - use direct
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 14:46:20 +0000 (15:46 +0100)]
sigh, no wrap - use direct

7 months agoadd ghdl wishbone basic test
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 14:01:40 +0000 (15:01 +0100)]
add ghdl wishbone basic test

7 months agocorrect iverilog script errors
Luke Kenneth Casson Leighton [Wed, 7 Apr 2021 11:50:34 +0000 (12:50 +0100)]
correct iverilog script errors

7 months agoadd verilator cocotb runner
Luke Kenneth Casson Leighton [Wed, 7 Apr 2021 11:49:55 +0000 (12:49 +0100)]
add verilator cocotb runner

7 months agoremove wb test from test.py
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 19:13:14 +0000 (20:13 +0100)]
remove wb test from test.py

7 months agoadd test wishbone (separate from test.py)
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 19:10:58 +0000 (20:10 +0100)]
add test wishbone (separate from test.py)

7 months agoFunction is a generator.
Staf Verhaegen [Tue, 6 Apr 2021 18:37:34 +0000 (20:37 +0200)]
Function is a generator.

7 months agoFix pre-layout simulation with 4K SRAM blocks.
Staf Verhaegen [Tue, 6 Apr 2021 18:33:58 +0000 (20:33 +0200)]
Fix pre-layout simulation with 4K SRAM blocks.

7 months agoAdd sim models for SRAM block.
Staf Verhaegen [Tue, 6 Apr 2021 18:32:12 +0000 (20:32 +0200)]
Add sim models for SRAM block.

Both Verilog and VHDL model is provided.

7 months agoadd wishbone sim gtk test script
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 16:09:34 +0000 (17:09 +0100)]
add wishbone sim gtk test script

7 months agoadd comments
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 15:07:42 +0000 (16:07 +0100)]
add comments

7 months agofix wishbone jtag test to run: results not correct yet
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:58:09 +0000 (15:58 +0100)]
fix wishbone jtag test to run: results not correct yet

7 months agoadd first cut at wishbone jtag unit test
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:38:31 +0000 (15:38 +0100)]
add first cut at wishbone jtag unit test

7 months agowhitespace
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:13:46 +0000 (15:13 +0100)]
whitespace

7 months ago80 char linewrap
Luke Kenneth Casson Leighton [Sun, 4 Apr 2021 18:09:18 +0000 (19:09 +0100)]
80 char linewrap

7 months agoTest different combinations of i, o, oe for InTriOut
Staf Verhaegen [Sun, 4 Apr 2021 16:06:42 +0000 (18:06 +0200)]
Test different combinations of i, o, oe for InTriOut

Now run_iverilog_ls180.py show the multiple drive conflict for
sram_dq_oe signal.

7 months agoSupport running tb on test_issuer subblock.
Staf Verhaegen [Sat, 3 Apr 2021 18:57:50 +0000 (20:57 +0200)]
Support running tb on test_issuer subblock.

Use wrapper class around dut that select proper signals depending on
top cell used. Should be able to be used later to extend to post_pnr
netlist.

7 months agoUpdate gitignore.
Staf Verhaegen [Sat, 3 Apr 2021 18:54:53 +0000 (20:54 +0200)]
Update gitignore.

8 months agoFull boundary scan.
Staf Verhaegen [Fri, 2 Apr 2021 18:27:08 +0000 (20:27 +0200)]
Full boundary scan.

Show that *pad__oe are x when they are set by boundary scan to 1.
Needs to be debugged.

8 months agoTypo.
Staf Verhaegen [Fri, 2 Apr 2021 17:28:57 +0000 (19:28 +0200)]
Typo.

8 months agoAdd helper class JTAGPin
Staf Verhaegen [Fri, 2 Apr 2021 17:11:04 +0000 (19:11 +0200)]
Add helper class JTAGPin

This will now group code for operation on pins.

8 months agoFirst version of boundary scan test bench.
Staf Verhaegen [Fri, 2 Apr 2021 16:16:23 +0000 (18:16 +0200)]
First version of boundary scan test bench.

Only for pre_pnr at the moment.

8 months agopre_pnr/test.py: Fix idcode SVF test name.
Staf Verhaegen [Fri, 2 Apr 2021 16:11:27 +0000 (18:11 +0200)]
pre_pnr/test.py: Fix idcode SVF test name.

8 months agopre_pnr/test.py: Reset JTAG before executing SVF.
Staf Verhaegen [Fri, 2 Apr 2021 16:10:24 +0000 (18:10 +0200)]
pre_pnr/test.py: Reset JTAG before executing SVF.

8 months agoTWI enabled in boundary scan
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:15:26 +0000 (23:15 +0100)]
TWI enabled in boundary scan

8 months agoshow how to get the boundary scan information from the JSON file
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:05:51 +0000 (23:05 +0100)]
show how to get the boundary scan information from the JSON file
generated by "make mkpinpux" in soc

8 months agoadd one more up to path
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 21:47:18 +0000 (22:47 +0100)]
add one more up to path

8 months agomove pre_pnr cocotb sim to soc-cocotb-sim directory
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 21:34:50 +0000 (22:34 +0100)]
move pre_pnr cocotb sim to soc-cocotb-sim directory

8 months agomove post-pnr to new subdirectory
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 21:29:35 +0000 (22:29 +0100)]
move post-pnr to new subdirectory

8 months agoupdate README
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 17:36:20 +0000 (18:36 +0100)]
update README

8 months agosort out Makefile for building
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:41:40 +0000 (17:41 +0100)]
sort out Makefile for building

8 months agoha! got IDCODE and reset test to work
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:35:04 +0000 (17:35 +0100)]
ha! got IDCODE and reset test to work

8 months agomatch ir_width with experiment10 and do not overwrite IDCODE
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:01:21 +0000 (17:01 +0100)]
match ir_width with experiment10 and do not overwrite IDCODE

8 months agoconnect up jtag corona pads
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:46:16 +0000 (15:46 +0100)]
connect up jtag corona pads

8 months agoadd cocotb testbench
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:42:17 +0000 (15:42 +0100)]
add cocotb testbench

8 months agoremove not-needed thing from cocotb Makefile
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:40:01 +0000 (15:40 +0100)]
remove not-needed thing from cocotb Makefile

8 months agoadd first cocotb Makefile
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:32:35 +0000 (15:32 +0100)]
add first cocotb Makefile

8 months agoadd "make corona" option
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:15:02 +0000 (15:15 +0100)]
add "make corona" option

8 months agocompile all libraries, use --std=08 it passes
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:03:32 +0000 (15:03 +0100)]
compile all libraries, use --std=08 it passes

8 months agoadd vst corrections program
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 13:40:06 +0000 (14:40 +0100)]
add vst corrections program

8 months agodo niolib conversion as well as nsxlib
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 11:19:14 +0000 (12:19 +0100)]
do niolib conversion as well as nsxlib

8 months agobuild vhd objects
Luke Kenneth Casson Leighton [Wed, 31 Mar 2021 17:36:38 +0000 (18:36 +0100)]
build vhd objects

8 months agoadd conversion from alliance vbe to vst using coriolis2 vasy
Luke Kenneth Casson Leighton [Wed, 31 Mar 2021 17:22:46 +0000 (18:22 +0100)]
add conversion from alliance vbe to vst using coriolis2 vasy

8 months agostart on Makefile, add notes, add alliance-check-toolkit submodule
Luke Kenneth Casson Leighton [Wed, 31 Mar 2021 17:07:53 +0000 (18:07 +0100)]
start on Makefile, add notes, add alliance-check-toolkit submodule

8 months agoadd vst to .gitignore so that generated files do not get added by mistake
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 12:36:09 +0000 (13:36 +0100)]
add vst to .gitignore so that generated files do not get added by mistake

8 months agoadd initial empty README.txt in ls180 directory
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 12:04:16 +0000 (13:04 +0100)]
add initial empty README.txt in ls180 directory