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last changeSat, 5 Jun 2021 18:30:08 +0000 (19:30 +0100)
shortlog
2021-06-05 Luke Kenneth... use git submodule soclayout for source files, rather... master
2021-06-05 Luke Kenneth... disallow adding verilog files
2021-06-05 Luke Kenneth... sort out build of chip/corona using experiments10_verilog
2021-06-04 Staf VerhaegenUse cocotb test on ls180/experiments9 with reconnected...
2021-04-17 Luke Kenneth... add verilator post-pnr cocotb sim
2021-04-17 Luke Kenneth... add chip conversion from ghdl to verilog
2021-04-17 Luke Kenneth... fix iovdd/iovss in-to-std_logic conversion
2021-04-16 Luke Kenneth... get pre-coriolis2 verilator (wishbone) functional
2021-04-16 Luke Kenneth... upload 32-bit wishbone data not 64-bit test data
2021-04-16 Luke Kenneth... corrections to wishbone test
2021-04-16 Luke Kenneth... corrections to wishbone test
2021-04-14 Luke Kenneth... add test boundary scan hard-coded test
2021-04-14 Luke Kenneth... try chip_r adder test (works)
2021-04-14 Luke Kenneth... remove async, use yield
2021-04-13 Luke Kenneth... get jtag tests running on basic adder
2021-04-13 Luke Kenneth... convert wb test to async
...
heads
5 months ago master