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use git submodule soclayout for source files, rather than
[soc-cocotb-sim.git]
/
ls180
/
post_pnr
/
cocotb_v
/
drwxr-xr-x
..
-rw-r--r--
289
Makefile
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-rw-r--r--
98
idcode.svf
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-rwxr-xr-x
902
run_verilator_chip.sh
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-rw-r--r--
8197
test.py
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projects / soc-cocotb-sim.git / tree