git.libre-soc.org Git - soc-cocotb-sim.git/tree

drwxr-xr-x		..
-rw-r--r--	10	.gitignore	blob \| history \| raw
-rw-r--r--	443	Makefile	blob \| history \| raw
-rw-r--r--	645	README.md	blob \| history \| raw
-rwxr-xr-x	44	clean.sh	blob \| history \| raw
-rw-r--r--	98	idcode.svf	blob \| history \| raw
-rwxr-xr-x	471	run_iverilog_ls180.sh	blob \| history \| raw
-rwxr-xr-x	373	run_iverilog_ti.sh	blob \| history \| raw
-rwxr-xr-x	458	run_iverilog_wb_ls180.sh	blob \| history \| raw
-rwxr-xr-x	742	run_verilator_ls180.sh	blob \| history \| raw
-rwxr-xr-x	713	run_verilator_wb_ls180.sh	blob \| history \| raw
-rw-r--r--	9193	test.py	blob \| history \| raw
-rw-r--r--	13768	testwb.py	blob \| history \| raw