more openpower import conversion
move over to from openpower imports
add icachemmu option to ISACaller
fix AttributeError in radixmmu testcase
Fix typo
End VL loop as soon as either src/dst step reaches VL Also, avoid incrementing dststep beyond VL-1
Fix typo
sort out predicate zeroing in ISACaller
attempting to add src/dest-zeroing to ISACaller
comments / code-shuffle
add twin-predicated extsw SVP64 ISACaller unit test
add SVP64 dststep incrementing in PowerDecoder2, Testissuer and ISACaller
add CR-based predication to ISACaller
add SVP64 INT-style predication to ISACaller
add instr_fetch mode to ISACaller Mem and RADIXMMU
add setvl unit test assertions, add 2nd test
get first revision setvl operational in ISACaller
include SVSTATE in namespace, passing to ISACaller
**FOR NOW** LD/ST relies on detection of twin-predication to determine if it should continue looping. this needs double-checking
add in SVP64 LD/ST basic test for ISACaller